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91. 发明授权

US09030237B2 Transistor circuit, flip-flop, signal processing circuit, driver circuit, and display device 有权
标题翻译：晶体管电路，触发器，信号处理电路，驱动电路和显示装置
公开(公告)号：US09030237B2
公开(公告)日：2015-05-12
申请号：US13818693
申请日：2011-09-01
申请人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
发明人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
IPC分类号： H03B1/00 , H03K3/00 , H03K17/687 , G09G3/36 , H03K19/017 , H01L27/12 , H03K3/356
CPC分类号： H03K17/687 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , H01L27/124 , H01L27/1255 , H03K3/356008 , H03K3/356026 , H03K19/01714
摘要： A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.
摘要翻译：晶体管电路包括至少一个晶体管，其中连接晶体管（Tr1）和电源线（33）的连接部分的至少一部分由形成晶体管（Tr1）的沟道的材料形成。该配置减小了晶体管电路的电路面积。

92. 发明授权

US08923472B2 Flip flop, shift register, driver circuit, and display device 有权
标题翻译：触发器，移位寄存器，驱动电路和显示设备
公开(公告)号：US08923472B2
公开(公告)日：2014-12-30
申请号：US13819046
申请日：2011-08-31
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
IPC分类号： G11C19/00 , H03K3/02 , G11C19/18 , G11C19/28 , G09G3/36
CPC分类号： H03K3/02 , G09G3/3677 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initialization section controlling the discharge section and the second output section. This makes it possible to realize a shift register capable of performing an all-ON operation regardless of clock signals.
摘要翻译：本发明的触发器包括：输入端子; 输出端子; 第一控制信号端和第二控制信号端; 第一输出部分，包括自举电容器，第一输出部分连接到第一控制信号端子和输出端子; 连接到第一输出部分源和输出端的第二输出部分; 连接到所述输入端子的第一输入部分，所述第一输入部分对所述自举电容器充电; 放电部，使自举电容器放电; 连接到所述输入端子的第二输入部分，所述第二输入部分也连接到所述第二输出部分; 控制所述放电部和所述第二输出部的复位部，所述复位部与所述第二控制信号端子连接; 控制所述第一输出部的第一初始化部; 控制所述第一输入部的第二初始化部; 以及控制排出部和第二输出部的第三初始化部。这使得可以实现无论时钟信号如何执行全导通操作的移位寄存器。

93. 发明授权

US08717273B2 Liquid crystal display device and drive method for liquid crystal display device 有权
标题翻译：液晶显示装置及液晶显示装置的驱动方法
公开(公告)号：US08717273B2
公开(公告)日：2014-05-06
申请号：US13395998
申请日：2010-06-25
申请人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Shuji Nishi , Seijirou Gyouten
发明人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Shuji Nishi , Seijirou Gyouten
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G2300/0842 , G09G2330/021 , G09G2340/0435 , G09G2360/144
摘要： A memory-type liquid crystal display device includes a liquid crystal panel including memory circuits, and conducts a refresh operation more than once during a display holding period after rewriting of a screen. The memory-type liquid crystal display device increases at least one of (i) a frequency at which the screen is rewritten and (ii) a frequency at which the refresh operation is conducted during the display holding period as an intensity of light received by the liquid crystal panel increases. This allows the memory-type liquid crystal display device to reduce power consumption while keeping its display quality.
摘要翻译：记忆型液晶显示装置包括具有存储电路的液晶面板，并且在重写画面之后的显示保持期间不止一次进行刷新动作。记忆型液晶显示装置增加以下至少一个：（i）画面重写的频率和（ii）在显示保持期间进行刷新操作的频率，作为由液晶面板增加。这使得存储型液晶显示装置在保持其显示质量的同时降低功耗。

94. 发明授权

US08665255B2 Power supply circuit and display device including the same 有权
标题翻译：电源电路和显示装置包括它们
公开(公告)号：US08665255B2
公开(公告)日：2014-03-04
申请号：US12733813
申请日：2008-07-24
申请人： Sachio Tsujino , Shuji Nishi , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
发明人： Sachio Tsujino , Shuji Nishi , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
IPC分类号： G09G5/00
CPC分类号： H02M3/073
摘要： An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between −VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively. In this arrangement, the driver section 11b generates signals each having a voltage alternating between VDD and 3VDD, as the control signals.
摘要翻译：本发明的目的是提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。在升压部（11a）中，电容器（C1）和（C2）分别具有与晶体管（Q1，Q3）和（Q2，Q4）相连的各自的第一端子。每个晶体管的栅极端子提供有在驱动器部分（11b）中产生的控制信号。驱动器部分（11b）包括与输入端子（Ti3，Ti4）连接的电容器（C3，C4），用于各自提供时钟信号DCK2，DCK2B各自具有在-VDD和VDD之间交替的电压（VDD表示来自外部的输入电源电压）作为分别提供给电容器（C1，C2）的第二端子的时钟信号DCK1，DCK1B的电平移位信号。在这种布置中，驱动器部分11b产生各自具有在VDD和3VDD之间交替的电压的信号作为控制信号。

95. 发明申请

US20130155044A1 SHIFT REGISTER, AND DISPLAY DEVICE 有权
标题翻译：移位寄存器和显示设备
公开(公告)号：US20130155044A1
公开(公告)日：2013-06-20
申请号：US13818462
申请日：2011-08-30
申请人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
发明人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
IPC分类号： G11C19/28
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286
摘要： A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.
摘要翻译：单元电路（11）包括：晶体管（T2），其漏极端子被提供有时钟信号（CK），其源极端子连接到输出端子（OUT）; 当提供有源全通控制信号（AON）时，将晶体管（T9）输出到输出端（OUT）的导通电压，并且当被提供有非活动全通控制信号（AONB）时，停止输出ON电压; 晶体管（T1），其根据输入信号（IN）将导通电压提供给晶体管（T2）的控制端子; 当提供有源全通控制信号（AON）时，晶体管（T4）向晶体管（T2）的控制端提供OFF电压。这使得可以提供能够防止在全部操作之后发生故障的简单结构的移位寄存器，并且提供显示装置。

96. 发明申请

US20130147524A1 TRANSISTOR CIRCUIT, FLIP-FLOP, SIGNAL PROCESSING CIRCUIT, DRIVER CIRCUIT, AND DISPLAY DEVICE 有权
标题翻译：晶体管电路，FLOP-FLOP，信号处理电路，驱动电路和显示装置
公开(公告)号：US20130147524A1
公开(公告)日：2013-06-13
申请号：US13818693
申请日：2011-09-01
申请人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
发明人： Takuya Hachida , Yasushi Sasaki , Yuhichiroh Murakami , Etsuo Yamamoto
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , H01L27/124 , H01L27/1255 , H03K3/356008 , H03K3/356026 , H03K19/01714
摘要： A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.
摘要翻译：晶体管电路包括至少一个晶体管，其中连接晶体管（Tr1）和电源线（33）的连接部分的至少一部分由形成晶体管（Tr1）的沟道的材料形成。该配置减小了晶体管电路的电路面积。

97. 发明授权

US08427206B2 Buffer and display device 有权
标题翻译：缓冲和显示设备
公开(公告)号：US08427206B2
公开(公告)日：2013-04-23
申请号：US12734691
申请日：2008-08-19
申请人： Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
发明人： Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
IPC分类号： H03K3/00
CPC分类号： G09G3/3677 , G09G2310/0291 , G09G2330/021 , H03K19/0013 , H03K19/01714 , H03K19/018507 , H03K19/09441
摘要： A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
摘要翻译：包括晶体管的单相输入，所述晶体管仅具有单一类型的沟道极性，该缓冲器包括：缓冲器部分32，包括由串联连接的两个n沟道晶体管构成的第一串联电路，第二系列由在连接点OUT处彼此串联连接的两个n沟道晶体管形成的电路，以及电容器; 以及反相信号生成部，用于从输入信号产生反相信号，所述反相信号生成部包括n沟道晶体管，但不包括p沟道晶体管，所述输入信号被输入到所述晶体管的各个栅极，所述反相信号生成部信号被输入到晶体管4的栅极，并且输出信号经由连接点OUT输出。使用缓冲器，可以减少消耗电流并且增加用于负载的电流驱动。

98. 发明授权

US08314648B2 Power supply circuit and display device including the same 有权
标题翻译：电源电路和显示装置包括它们
公开(公告)号：US08314648B2
公开(公告)日：2012-11-20
申请号：US12734394
申请日：2008-09-01
申请人： Shuji Nishi , Sachio Tsujino , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
发明人： Shuji Nishi , Sachio Tsujino , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/077
摘要： An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.
摘要翻译：本发明的一个实施例提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。当在升压部中的第一电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第三电容器，进一步升高电压，从而导通第一晶体管。当在升压部中的第二电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第四电容器，进一步升压电压，从而导通第二晶体管。这种布置消除了用作输出侧开关元件的第一和第二晶体管中的阈值电压下降的问题。

99. 发明授权

US08344988B2 Signal output circuit, shift register, output signal generating method, display device driving circuit, and display device 有权
标题翻译：信号输出电路，移位寄存器，输出信号生成方法，显示装置驱动电路和显示装置
公开(公告)号：US08344988B2
公开(公告)日：2013-01-01
申请号：US11922345
申请日：2006-07-13
申请人： Etsuo Yamamoto , Yuhichiroh Murakami , Eiji Matsuda
发明人： Etsuo Yamamoto , Yuhichiroh Murakami , Eiji Matsuda
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G5/001 , G11C19/28
摘要： A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
摘要翻译：本发明的一个实施例的信号输出电路设置在移位寄存器的单元级中。信号输出电路包括设置复位触发器和信号产生电路，用于根据输入的信号通过加载或阻塞时钟信号来产生输出信号。信号输出电路被布置为：信号发生电路接收从触发器输出的信号和反馈到信号发生电路的输出信号; 并将输出信号反馈到触发器的复位输入。这使得可以实现电路面积的减小和电路的简化。

100. 发明申请

US20090267924A1 Drive Circuit, Display Device Provided With Such Drive Circuit and Method for Driving Display Device 有权
标题翻译：驱动电路，具有这种驱动电路的显示装置和驱动显示装置的方法
公开(公告)号：US20090267924A1
公开(公告)日：2009-10-29
申请号：US12085925
申请日：2006-09-07
申请人： Shinsaku Shimizu , Yuhichiroh Murakami
发明人： Shinsaku Shimizu , Yuhichiroh Murakami
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： While an output signal of a flip-flop is inactive in a shift register, NAND circuits of clock pulse extracting sections prevent the performing of conduction switching operation in accordance with periodic level change of clock signals between a logical derivation path for High output and a logical derivation path for Low output, by input of the output signal.
摘要翻译：虽然触发器的输出信号在移位寄存器中不起作用，但是时钟脉冲提取部分的NAND电路根据用于高输出的逻辑导出路径和逻辑的逻辑导出路径之间的时钟信号的周期性电平改变来阻止执行导通切换操作通过输出信号输入低输出的推导路径。

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