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91. 发明授权

US08336020B2 Computing device and method for inspecting layout of printed circuit board 失效
标题翻译：用于检查印刷电路板布局的计算装置和方法
公开(公告)号：US08336020B2
公开(公告)日：2012-12-18
申请号：US13213072
申请日：2011-08-18
申请人： Dan-Chen Wu , Shou-Kuo Hsu , Cheng-Hsien Lee , Chun-Jen Chen
发明人： Dan-Chen Wu , Shou-Kuo Hsu , Cheng-Hsien Lee , Chun-Jen Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
摘要翻译：在用于检查印刷电路板（PCB）的布局的方法中，从PCB的电子布局图确定要检查的部件，并且可以选择可用于该部件的输电线。检查布局图以确定组件是否连接到电力传输线，并进一步检查以确定组件的多个接地引脚是否连接到电力传输线。如果多个接地引脚连接到电力传输线，则确定由组件的两个或更多个接地引脚共享的通孔。共享通孔在布局图上标出。

92. 发明授权

US08283994B2 Differential signal transmission device 失效
标题翻译：差分信号传输装置
公开(公告)号：US08283994B2
公开(公告)日：2012-10-09
申请号：US12560445
申请日：2009-09-16
申请人： Shou-Kuo Hsu , Cheng-Hsien Lee , Ying-Tso Lai , Hsiao-Yun Su , Jia-Chi Chen
发明人： Shou-Kuo Hsu , Cheng-Hsien Lee , Ying-Tso Lai , Hsiao-Yun Su , Jia-Chi Chen
IPC分类号： H03H7/38
CPC分类号： H04L25/0272
摘要： A differential signal transmission device transmits N differential signal pairs from a differential signal generator to a number of receiving terminals. The N differential signal pairs include N positive signals and N negative signals. The N positive signals are clustered at a first positive clustering point. The first positive clustering point is connected to a second positive clustering point via a first matching resistor. The second positive clustering point is grounded via a first grounding resistor, and outputs a number of positive signals to the number of receiving terminals respectively. The N negative signals are clustered at a first negative clustering point. The first negative clustering point is connected to a second negative clustering point via a second matching resistor. The second negative signal clustering point is grounded via a second grounding resistor, and outputs a number of negative signals to the number of receiving terminals respectively.
摘要翻译：差分信号传输装置将差分信号发生器的N个差分信号对发送到多个接收终端。 N个差分信号对包括N个正信号和N个负信号。 N个正信号聚集在第一个正聚类点。第一正聚集点通过第一匹配电阻连接到第二正聚集点。第二个正聚集点通过第一接地电阻接地，并分别输出多个正信号到接收端的数量。 N个负信号聚集在第一个负聚类点。第一负聚集点通过第二匹配电阻器连接到第二负聚集点。第二负信号聚簇点通过第二接地电阻接地，并分别输出多个负信号至接收端数。

93. 发明授权

US08247704B2 Motherboard interconnection device 有权
标题翻译：主板互连设备
公开(公告)号：US08247704B2
公开(公告)日：2012-08-21
申请号：US12503680
申请日：2009-07-15
申请人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
发明人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K3/30
CPC分类号： H05K1/0239 , H05K1/0245 , H05K1/0295 , H05K1/113 , H05K3/429 , H05K2201/044 , H05K2201/09254 , H05K2201/10015 , H05K2201/10545 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
摘要： A motherboard interconnection device includes a top layer, a bottom layer, a first and a third electronic elements positioned on the top layer, and a second and a fourth electronic elements positioned on the bottom layer. A first end of the first electronic element on the top layer is connected to the first end of the second electronic element on the bottom layer with a first via hole, and the first end of the third electronic element on the top layer is connected to the first end of the fourth electronic element on the bottom layer with a second via hole. The second ends of the two electronic elements on the top layer are connected to a first part, and the second ends of the two electronic elements on the bottom layer are connected to a second part.
摘要翻译：母板互连装置包括顶层，底层，位于顶层上的第一和第三电子元件以及位于底层上的第二和第四电子元件。顶层上的第一电子元件的第一端通过第一通孔连接到底层上的第二电子元件的第一端，并且顶层上的第三电子元件的第一端连接到第四电子元件的第一端部具有第二通孔。顶层上的两个电子元件的第二端连接到第一部分，底层上的两个电子元件的第二端连接到第二部分。

94. 发明授权

US08194412B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08194412B2
公开(公告)日：2012-06-05
申请号：US12647395
申请日：2009-12-25
申请人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K1/16 , H05K7/00
CPC分类号： H05K1/0253 , H05K1/181 , H05K2201/09381 , H05K2201/0969 , H05K2201/10015 , H05K2201/10022 , H05K2201/10636 , Y02P70/611
摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8 ⁢ Wpad + 10 ⁢ T 0.8 ⁢ Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.
摘要翻译：印刷电路板包括信号平面和参考平面。信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。参考平面为通过无源元件和信号传输线传输的信号提供返回路径。在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8Wpad+ 10T 0.8Wtrace + T，其中Wpad是焊盘的宽度，Wtrace是传输线的宽度，T是焊盘的高度。

95. 发明授权

US08058557B2 Printed circuit board 失效
标题翻译：印刷电路板
公开(公告)号：US08058557B2
公开(公告)日：2011-11-15
申请号：US11957416
申请日：2007-12-15
申请人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
发明人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672
摘要： An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.
摘要翻译：示例性PCB包括第一参考层，第一信号层，第二信号层和第三信号层，第一差分对以边缘耦合结构布置在第一信号层中，并参考第一参考层第一信号层和第二信号层之间的距离大于第一参考层和第一信号层之间的距离，第二差分对被布置在第二信号层中，第三信号层以广泛耦合结构。 PCB具有传输线高密度布局。

96. 发明授权

US08022309B2 Flexible printed circuit board 失效
标题翻译：柔性印刷电路板
公开(公告)号：US08022309B2
公开(公告)日：2011-09-20
申请号：US11946859
申请日：2007-11-29
申请人： Yu-Chang Pai , Shou-Kuo Hsu , Chien-Hung Liu
发明人： Yu-Chang Pai , Shou-Kuo Hsu , Chien-Hung Liu
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K1/0224 , H05K1/0253 , H05K1/0393 , H05K2201/09236 , H05K2201/09336 , H05K2201/0969 , Y10T29/49156
摘要： An exemplary FPCB includes a signal layer having a differential pair consisting of two transmission lines arranged therein, a ground layer, and a dielectric layer lying between the signal layer and the ground layer. Two sheets made of conductive materials are respectively arranged at opposite sides of the differential pair, and both connected to ground. The sheets are apart from and parallel to the transmission lines. The ground layer has a void defined therein, and the void is located under the two transmission lines.
摘要翻译：示例性FPCB包括具有由布置在其中的两条传输线组成的差分对的信号层，接地层和位于信号层和接地层之间的电介质层。由导电材料制成的两片分别布置在差动对的相对两侧，并且都连接到地面。纸张与传输线分开并平行。接地层具有限定在其中的空隙，并且空隙位于两条传输线之下。

97. 发明授权

US07817487B2 Motherboard with voltage regulator for supporting DDR2 memory modules and DDR3 memory modules 有权
标题翻译：具有稳压器的主板，用于支持DDR2内存模块和DDR3内存模块
公开(公告)号：US07817487B2
公开(公告)日：2010-10-19
申请号：US11952140
申请日：2007-12-07
申请人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Duen-Yi Ho , Cheng-Shien Li
IPC分类号： G11C5/14
CPC分类号： G06F1/26 , G11C5/04 , G11C5/147 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.
摘要翻译：示例性主板包括驱动模块，布置成用于安装第一类型存储器并经由第一通道连接到驱动模块的第一插槽模块，布置成用于安装第二类型存储器并连接到驱动模块的第二插槽模块，其经由第二通道和电连接到第一插槽模块和第二插槽模块的电压调节器。第一存储器和第二存储器替代地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

98. 发明授权

US07781680B2 Flexible printed circuit board 有权
标题翻译：柔性印刷电路板
公开(公告)号：US07781680B2
公开(公告)日：2010-08-24
申请号：US11951290
申请日：2007-12-05
申请人： Yu-Chang Pai , Shou-Kuo Hsu , Chien-Hung Liu
发明人： Yu-Chang Pai , Shou-Kuo Hsu , Chien-Hung Liu
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K1/0393 , H05K2201/09236 , H05K2201/09318 , H05K2201/09336 , H05K2201/09672
摘要： An exemplary FPCB includes a differential pair consisting of a first transmission line and a second transmission line, a signal layer with the first transmission line arranged therein, a ground layer having a void which includes the area beneath the first transmission line, and a dielectric layer lying between the signal layer and the ground layer. The second transmission line is arranged in the ground layer offset from the first transmission line in the horizontal direction. The FPCB can transmit high speed signals.
摘要翻译：示例性FPCB包括由第一传输线和第二传输线组成的差分对，其中布置有第一传输线的信号层，具有包括第一传输线下面的区域的空隙的接地层，以及介电层位于信号层和接地层之间。第二传输线布置在沿水平方向偏离第一传输线的接地层中。 FPCB可以传输高速信号。

99. 发明授权

US07752348B2 Motherboard for supporting different types of memories 失效
标题翻译：主板支持不同类型的记忆
公开(公告)号：US07752348B2
公开(公告)日：2010-07-06
申请号：US11952139
申请日：2007-12-07
申请人： Chun-Sheng Chen , Shou-Kuo Hsu , Cheng-Shien Li , Duen-Yi Ho , Yu-Chang Pai
发明人： Chun-Sheng Chen , Shou-Kuo Hsu , Cheng-Shien Li , Duen-Yi Ho , Yu-Chang Pai
IPC分类号： G06F3/00 , H05K7/10
CPC分类号： H05K1/0295 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： A motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulating circuit electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulating circuit detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.
摘要翻译：主板包括布置成用于安装第一类型存储器的第一插槽，布置用于安装第二类型存储器的第二插槽以及电连接到第一插槽和第二插槽的电压调节电路。第一存储器和第二存储器替代地安装在母板上，电压调节电路检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

100. 发明授权

US07599826B2 System and method for generating various simulation conditions for simulation analysis 失效
标题翻译：用于生成模拟分析的各种仿真条件的系统和方法
公开(公告)号：US07599826B2
公开(公告)日：2009-10-06
申请号：US11309042
申请日：2006-06-13
申请人： Shou-Kuo Hsu , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Cheng-Shien Li
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module (301) for generating an N-bit binary sequence consisting of “1” and “0” according to signal source parameters; a application module (302) for applying the N-bit binary sequence to generate the various simulation conditions according to control parameters; a noise generating module (303) for generating N influence values of Gauss noises with N standard deviations to N signal bit-widths; and an addition module (304) for adding the Gauss noises to corresponding digital waveform positions of the generated simulation conditions. A related method is also disclosed.
摘要翻译：公开了一种用于生成用于模拟分析的各种模拟条件的系统。该系统包括：根据信号源参数产生由“1”和“0”组成的N位二进制序列的信号产生模块（301）应用模块（302），用于根据控制参数应用所述N位二进制序列以产生各种仿真条件; 噪声产生模块（303），用于产生具有N个标准偏差N个信号位宽的高斯噪声的N个影响值; 以及用于将高斯噪声加到所产生的模拟条件的相应数字波形位置的加法模块（304）。还公开了相关方法。

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