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91. 发明申请

US20060046494A1 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060046494A1
公开(公告)日：2006-03-02
申请号：US11114083
申请日：2005-04-26
申请人： Ki-Won Nam
发明人： Ki-Won Nam
IPC分类号： H01L21/461
CPC分类号： H01L21/76838 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： The present invention relates to a method for fabricating a semiconductor device with a fine pattern even without decreasing a line width of a photoresist pattern. The method includes the steps of: forming a target etching layer on a substrate; forming a plurality of etch mask patterns with high pattern density in a first region and a low pattern density in a second region on the target etching layer; removing a native oxide layer grown on the target etching layer such that a line width of each etch mask pattern decreases in more extents in the second region than in the first region; and etching the target etching layer by using the plurality of etch mask patterns as a mask.
摘要翻译：本发明涉及一种即使不减少光致抗蚀剂图案的线宽也可以精细图案制造半导体器件的方法。该方法包括以下步骤：在衬底上形成靶蚀刻层; 在目标蚀刻层的第二区域中形成在第一区域中具有高图案密度和低图案密度的多个蚀刻掩模图案; 去除在目标蚀刻层上生长的自然氧化物层，使得每个蚀刻掩模图案的线宽在第二区域中比在第一区域中更大程度地减小; 并通过使用多个蚀刻掩模图案作为掩模蚀刻目标蚀刻层。

92. 发明申请

US20050287809A1 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region 失效
标题翻译：制造能够减小外围区域临界尺寸的半导体器件的方法
公开(公告)号：US20050287809A1
公开(公告)日：2005-12-29
申请号：US11165740
申请日：2005-06-24
申请人： Kyung-Won Lee , Ki-Won Nam
发明人： Kyung-Won Lee , Ki-Won Nam
IPC分类号： H01L21/8242 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/32 , H01L21/3213
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/32139 , H01L27/10894
摘要： A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
摘要翻译：一种半导体器件的制造方法，其中周边区域的临界尺寸减小。该方法包括以下步骤：在包括单元区域和周边区域的基板上形成氮化硅层; 在氮化硅层上形成氮氧化硅层; 在氮氧化硅层上形成线型光致抗蚀剂图案，使得单元区域中的光致抗蚀剂图案的宽度大于最终图案结构的宽度，并且周边区域中的光致抗蚀剂图案具有减小图案崩溃的发生率的宽度 ; 通过抑制聚合物的产生，蚀刻硅氧氮化物层和氮化硅层，直到剩余的氮氧化硅层和剩余的氮化硅层的宽度小于用作蚀刻掩模的光致抗蚀剂图案的宽度; 并过剩蚀刻剩余的氮化硅层。

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