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91. 发明授权

US07937563B2 Voltage droop mitigation through instruction issue throttling 有权
标题翻译：通过指导问题调节减小电压下降
公开(公告)号：US07937563B2
公开(公告)日：2011-05-03
申请号：US12127514
申请日：2008-05-27
申请人： Samuel D. Naffziger , Michael Gerard Butler
发明人： Samuel D. Naffziger , Michael Gerard Butler
IPC分类号： G06F9/30 , G06F9/40 , G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F9/3836 , G06F9/3869
摘要： A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold.
摘要翻译：一种用于提供数字实时电压下降检测和随后的电压下降降低的系统和方法。保留站内的调度器可以存储对应于从硅硅功率建模分析得到的指令的节点电容切换活动的每个指令的权重值。对于使用可用源数据选择的指令，将相应的权重值相加在一起以产生局部电流消耗值，并将该值与来自产生活动事件的其他处理器核心的相应调度器的任何现有全局电流消耗值相加。活动事件被存储。调度程序中的散列函数用于使用计算的活动事件和存储的较旧活动事件来确定最近和旧活动平均值。如果旧活动平均值与近期活动平均值之间的差异超过第一阈值或近期活动平均值超过第二阈值，就会发生指令问题调节。

92. 发明授权

US07844838B2 Inter-die power manager and power management method 有权
标题翻译：芯片间电源管理器和电源管理方法
公开(公告)号：US07844838B2
公开(公告)日：2010-11-30
申请号：US11589573
申请日：2006-10-30
申请人： Samuel D. Naffziger , Christopher A. Poirier
发明人： Samuel D. Naffziger , Christopher A. Poirier
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.
摘要翻译：本文公开了用于管理模块电源的设备和方法。在一个实施例中，模块包括第一管芯; 第二个死亡和电源经理。电源管理器监视第一管芯和第二管芯的功率要求，并根据电源要求为第一管芯和第二管芯分配电源。

93. 发明授权

US07772906B2 Low power flip flop through partially gated slave clock 有权
标题翻译：低功率触发器通过部分门控从时钟
公开(公告)号：US07772906B2
公开(公告)日：2010-08-10
申请号：US12100040
申请日：2008-04-09
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/012 , H03K5/135
摘要： A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced.
摘要翻译：一种用于降低半导体芯片上的触发器电路内的功耗的系统和方法。门锁输入时钟信号由从锁存器接收。门控输入时钟源自非门控输入时钟信号和时钟门控条件。时钟门控条件确定触发器的输入数据信号和从锁存器的存储内部状态何时具有相同的逻辑值，例如仅逻辑低电平值。如果它们具有相同的值，则从锁存器不接收到非门控输入时钟信号的切换，从锁存器的内部节点的信号切换被减少，并且功耗降低。

94. 发明授权

US07772889B2 Programmable sample clock for empirical setup time selection 有权
标题翻译：用于经验设置时间选择的可编程采样时钟
公开(公告)号：US07772889B2
公开(公告)日：2010-08-10
申请号：US12100052
申请日：2008-04-09
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H03K19/00 , H03K3/289 , G06F7/38
CPC分类号： H03K3/35625 , H03K3/0375
摘要： A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon.
摘要翻译：一种用于有效改进更快处理器设计的时序分析的系统和方法，对芯片面积的影响可以忽略不计。不是为半导体芯片上的触发器电路提供单个时钟，而是使用分离时钟。触发器接收主锁存器的主时钟信号，并为从锁存器接收单独的从时钟信号。主和从时钟门控电路耦合到全局时钟分配系统和本地触发器。主时钟门电路接收用于选择延迟的延迟控制信号，其中所选择的延迟确定主时钟信号在从时钟信号转变之后转变的附加时间量。在半导体芯片上使用延迟的主时钟可以允许定时路径具有更多的计算时间而不增加时钟周期时间。此外，可以选择延迟来固定后硅中的定时路径。

95. 发明申请

US20090249149A1 LOW OVERHEAD SOFT ERROR TOLERANT FLIP FLOP 有权
标题翻译： LOW OVERHEAD SOFT错误容许FLIP FLOP
公开(公告)号：US20090249149A1
公开(公告)日：2009-10-01
申请号：US12059543
申请日：2008-03-31
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： G06F11/07
CPC分类号： H03K19/007 , H03K3/037
摘要： A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal.
摘要翻译：触发器内的软错误恢复（SER）的系统和方法。触发器的第一级接收非门控输入时钟信号。触发器的第二级接收门控输入时钟信号。第二阶段还可以在单独的节点上存储预缓冲数据输出和一个或多个反馈存储值。触发器具有用于恢复预缓冲数据输出和任何反馈存储值的SER电路，而不需要时钟信号的转换。

96. 发明授权

US07447941B2 Error recovery systems and methods for execution data paths 失效
标题翻译：错误恢复系统和执行数据路径的方法
公开(公告)号：US07447941B2
公开(公告)日：2008-11-04
申请号：US11184318
申请日：2005-07-19
申请人： Samuel D. Naffziger , Don C. Soltis, Jr.
发明人： Samuel D. Naffziger , Don C. Soltis, Jr.
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3012 , G06F9/3826 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.
摘要翻译：公开了一种用于多核处理器的整数执行单元中的错误恢复的系统和方法。在示例性实施例中，方法可以包括检查具有并行数据寄存器的执行数据路径中的事务的奇偶校验。如果奇偶校验失败，该方法还可以包括将并行数据寄存器中的一个复制到损坏的数据寄存器。

97. 发明授权

US07323920B2 Soft-error rate improvement in a latch using low-pass filtering 有权
标题翻译：使用低通滤波的锁存器中的软错误率改进
公开(公告)号：US07323920B2
公开(公告)日：2008-01-29
申请号：US11152274
申请日：2005-06-13
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356104
摘要： In a preferred embodiment, the invention provides a circuit and method for reducing soft error events in latches. A low-pass filter is placed between the output of a forward inverter and the inputs of a feedback keeper. The first and second outputs of the low-pass filter are connected to first and second inputs respectively of the feedback keeper. The only type of diffusion connected to the first output of the low-pass filter is a P-type diffusion. The only type of diffusion connected to the second output of the low-pass filter is an N-type diffusion. The feedback keeper is connected to an input of the forward inverter.
摘要翻译：在优选实施例中，本发明提供了用于减少锁存器中的软错误事件的电路和方法。在正向逆变器的输出端和反馈保持器的输入端之间放置一个低通滤波器。低通滤波器的第一和第二输出分别连接到反馈保持器的第一和第二输入端。连接到低通滤波器的第一输出的唯一类型的扩散是P型扩散。连接到低通滤波器的第二输出的唯一类型的扩散是N型扩散。反馈控制器连接到正向逆变器的输入。

98. 发明授权

US07321482B2 Sub-circuit voltage manipulation 失效
标题翻译：子电路电压操作
公开(公告)号：US07321482B2
公开(公告)日：2008-01-22
申请号：US10804624
申请日：2004-03-19
申请人： Don Douglas Josephson , Samuel D. Naffziger
发明人： Don Douglas Josephson , Samuel D. Naffziger
IPC分类号： H02H9/00 , G01R19/18 , G01R19/22
CPC分类号： G01R31/3161 , G01R31/3004 , G01R31/31721 , H03K5/08
摘要： An integrated circuit is provided which in one embodiment includes a first sub-circuit coupled to a first power supply rail providing a first power supply voltage; a second sub-circuit coupled to a second power supply rail providing a second power supply voltage; and first power supply modulation means, coupled to the first sub-circuit, for modulating the first power supply voltage without modulating the second power supply voltage.
摘要翻译：提供一种集成电路，其在一个实施例中包括耦合到提供第一电源电压的第一电源轨的第一子电路; 耦合到提供第二电源电压的第二电源轨的第二子电路; 以及耦合到第一子电路的用于调制第一电源电压而不调制第二电源电压的第一电源调制装置。

99. 发明授权

US07224563B2 Method and device for circuit control 有权
标题翻译：电路控制方法和装置
公开(公告)号：US07224563B2
公开(公告)日：2007-05-29
申请号：US10651360
申请日：2003-08-29
申请人： Samuel D. Naffziger
发明人： Samuel D. Naffziger
IPC分类号： H02H7/00
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： One disclosed embodiment of the invention is directed to circuit control that comprises sensing a delivered voltage to a portion of an integrated circuit, determining an appropriate frequency for the portion of the integrated circuit, and providing the appropriate frequency to the integrated circuit.
摘要翻译：本发明的一个公开的实施例涉及电路控制，其包括感测到集成电路的一部分的传送电压，确定集成电路的该部分的适当频率，以及向集成电路提供适当的频率。

100. 发明授权

US07148755B2 System and method to adjust voltage 失效
标题翻译：系统和方法来调节电压
公开(公告)号：US07148755B2
公开(公告)日：2006-12-12
申请号：US10648570
申请日：2003-08-26
申请人： Samuel D. Naffziger , Shahram Ghahremani , Christopher A. Poirier
发明人： Samuel D. Naffziger , Shahram Ghahremani , Christopher A. Poirier
IPC分类号： H01L7/16 , H03J7/04
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0992
摘要： A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.
摘要翻译：可用于实现电压调整（例如，用于集成电路）的系统和方法。在一个实施例中，该系统包括提供具有基于工作电压而变化的频率的时钟信号的频率发生器。该系统还包括控制器，其提供控制信号以根据对时钟信号的频率的调整来调整工作电压。

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