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91. 发明授权

US06380570B1 Gate overvoltage control networks 有权
标题翻译：门过压控制网络
公开(公告)号：US06380570B1
公开(公告)日：2002-04-30
申请号：US09556211
申请日：2000-04-21
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L2972
CPC分类号： H01L27/0251
摘要： A semiconductor device which comprises an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region comprises at least a gate dielectric; and an overvoltage control network coupled to the gate dielectric of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said gated device.
摘要翻译：一种半导体器件，包括第一导电类型的阳极; 第二导电类型的阴极; 分离所述阳极和所述阴极的器件区域，所述器件区域至少包括栅极电介质; 以及耦合到所述器件区域的栅极电介质的过电压控制网络，其中所述过电压控制网络基本上减小所述门控器件的电应力。

92. 发明授权

US06236103B1 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06236103B1
公开(公告)日：2001-05-22
申请号：US09283828
申请日：1999-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

93. 发明授权

US6096584A Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region 失效
标题翻译：绝缘体上硅和CMOS-on-SOI双膜制造工艺，具有共面的硅和隔离层，并在一个区域上添加第二硅层
公开(公告)号：US6096584A
公开(公告)日：2000-08-01
申请号：US38936
申请日：1998-03-12
申请人： John J. Ellis-Monaghan , Steven H. Voldman
发明人： John J. Ellis-Monaghan , Steven H. Voldman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/786 , H01L21/00
CPC分类号： H01L27/0251 , H01L21/84 , H01L27/1203
摘要： Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.
摘要翻译：在制造所选择的电子部件（包括电阻器，电容器和二极管）期间，在硅绝缘体（SOI）衬底上的选定位置处形成硅。使用图案化的可移除掩模限定硅位置，并且可以通过沉积或生长来施加硅，并且可以采用多晶硅或晶体硅的形式。通过在选定区域中具有厚的双层硅，显着改善了SOI器件的静电放电（ESD）特性。

94. 发明授权

US06071803A Electrical contact to buried SOI structures 失效
标题翻译：电接触埋入SOI结构
公开(公告)号：US06071803A
公开(公告)日：2000-06-06
申请号：US192586
申请日：1998-11-17
申请人： Matthew J. Rutten , Steven H. Voldman
发明人： Matthew J. Rutten , Steven H. Voldman
IPC分类号： H01L21/768 , H01L21/336 , H01L21/84 , H01L23/52 , H01L27/12 , H01L29/78 , H01L29/786 , H01L21/00 , H01L21/4763
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203 , H01L2924/0002
摘要： Electrically conductive studs are employed to interconnect bulk active devices and SOI devices in a semiconductor device. Also provided is a method for fabricating such devices.
摘要翻译：导电柱用于在半导体器件中互连体积有源器件和SOI器件。还提供了一种用于制造这种装置的方法。

95. 发明授权

US5882967A Process for buried diode formation in CMOS 失效
标题翻译： CMOS中埋入二极管形成工艺
公开(公告)号：US5882967A
公开(公告)日：1999-03-16
申请号：US852850
申请日：1997-05-07
申请人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
发明人： Jeffrey S. Brown , Steven J. Holmes , Robert K. Leidy , Steven H. Voldman
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092 , H01L29/866 , H01L21/8234
CPC分类号： H01L27/0255 , H01L21/8238
摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.
摘要翻译：根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

96. 发明授权

US5637912A Three-dimensional monolithic electronic module having stacked planar arrays of integrated circuit chips 失效
标题翻译：具有集成电路芯片的堆叠平面阵列的三维单片电子模块
公开(公告)号：US5637912A
公开(公告)日：1997-06-10
申请号：US653752
申请日：1996-05-31
申请人： Martha A. C. Cockerill , John G. Maltabes , Loretta J. O'Connor , Steven H. Voldman
发明人： Martha A. C. Cockerill , John G. Maltabes , Loretta J. O'Connor , Steven H. Voldman
IPC分类号： H01L25/00 , H01L21/66 , H01L21/98 , H01L25/065 , H01L27/00
CPC分类号： H01L25/50 , H01L22/20 , H01L25/0657 , H01L2225/06524 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002
摘要： A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
摘要翻译：一种制造方法和合成的单片电子模块，其包括多个堆叠的平面扩展阵列的集成电路芯片。该制造方法包括将集成电路芯片的晶片切割成多个集成电路芯片阵列。然后将集成电路芯片的阵列堆叠以形成电子模块。金属化图案可以沉积在电子模块的基本平坦的表面上，并且用于互连其中包含的各种集成电路芯片阵列。阐述制造方法和结果多芯片封装的具体细节。

97. 发明授权

US5625280A Voltage regulator bypass circuit 失效
标题翻译：电压调节器旁路电路
公开(公告)号：US5625280A
公开(公告)日：1997-04-29
申请号：US550423
申请日：1995-10-30
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H02H9/04 , H02H9/00 , H02H3/24
CPC分类号： H02H9/046 , H02H9/041
摘要： An on-chip voltage regulator circuit isolates the chip circuitry from spurious signals and electrostatic discharge (ESD) of peripheral circuitry. A bypass function for the regulator circuit is initiated on detection of the onset of an over voltage condition. In one implementation, a MOSFET is used to (1) initiate a parallel current path from Vcc to Vdd and (2) bypass the regulator to establish a continuous current path from the ESD diode to the Vcc to the Vdd power grid. The circuit addresses level shifting and uses an RC triggering technique.
摘要翻译：片内稳压电路将芯片电路与外设电路的杂散信号和静电放电（ESD）隔离开来。在检测过电压状态的开始时，启动调节器电路的旁路功能。在一个实现中，使用MOSFET来（1）启动从Vcc到Vdd的并联电流路径，（2）旁路调节器以建立从ESD二极管到Vcc到Vdd电网的连续电流路径。该电路解决电平移位并使用RC触发技术。

98. 发明授权

US5559051A Process for manufacturing a silicon chip with an integrated magnetoresistive head mounted on a slider 失效
标题翻译：用于制造具有安装在滑块上的集成磁阻头的硅芯片的工艺
公开(公告)号：US5559051A
公开(公告)日：1996-09-24
申请号：US363465
申请日：1994-12-23
申请人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
发明人： Steven H. Voldman , Albert J. Wallash , Reginald B. Wilcox, Jr.
IPC分类号： G11B5/39 , G11B5/31 , G11B5/40 , G11B5/48 , G11B33/12 , H01L21/28 , H01L21/301 , H01L21/304 , H01L21/48
CPC分类号： G11B5/40 , G11B5/3106 , G11B33/12 , G11B5/3967 , G11B5/4806 , Y10T29/49034 , Y10T29/49041
摘要： A process of making an MR head having its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the row level to ultimate completion of individual sliders. A silicon wafer, including the integrated circuit devices, is sliced into a plurality of silicon bars, each bar including a row of circuit devices. A plurality of rows and columns of MR heads are constructed on a ceramic wafer. The ceramic wafer is then also sliced into bars, each bar including a row of MR heads. Each silicon bar is then bonded to a ceramic bar, forming composite bars of MR heads electrically connected to the circuit devices. Each composite bar is then further processed and diced into individual sliders, each slider carrying an MR head which is ESD protected.
摘要翻译：制造具有其MR条纹的MR头的过程，其保护不受诸如碳化钛的滑块上的静电放电（ESD）的影响。 MR条纹由多个硅集成电路器件保护，这些硅集成电路器件将MR感应电流从MR条纹传导到MR头中的较大部件，例如第一和第二屏蔽层和线圈层。在优选实施例中，集成电路器件和互连构造在单晶硅芯片中。硅芯片固定地安装在滑块的后缘，并且MR磁头安装在硅芯片的与集成电路器件相邻的后缘。本发明包括通过将用于制造MR磁头的薄膜技术与用于制造集成电路器件的集成电路技术结合在一起来批量生产滑块的方法。这些技术在行级结合到最终完成各个滑块。包括集成电路器件的硅晶片被切成多个硅棒，每个棒包括一排电路器件。在陶瓷晶片上构造多个行和列的MR磁头。然后将陶瓷晶片切成棒，每个棒包括一排MR头。然后将每个硅棒结合到陶瓷棒，形成电连接到电路装置的MR头的复合棒。然后将每个复合棒进一步处理并切割成各个滑块，每个滑块承载ESD保护的MR头。

99. 发明授权

US08946013B2 Lateral diffusion field effect transistor with drain region self-aligned to gate electrode 有权
标题翻译：侧向扩散场效应晶体管，漏极区自对准至栅电极
公开(公告)号：US08946013B2
公开(公告)日：2015-02-03
申请号：US13364663
申请日：2012-02-02
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/00 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

100. 发明授权

US08487379B2 Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications 有权
标题翻译： SOI / RF SiGe应用的超高电阻率晶圆掩埋电感的结构和方法
公开(公告)号：US08487379B2
公开(公告)日：2013-07-16
申请号：US13453426
申请日：2012-04-23
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

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