专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06606702B1 Multiprocessor speculation mechanism with imprecise recycling of storage operations 有权
标题翻译：多处理器推测机制，存储操作不正确的回收
公开(公告)号：US06606702B1
公开(公告)日：2003-08-12
申请号：US09588606
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/52 , G06F9/522
摘要： Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is received for execution. In response to the barrier instruction, a barrier operation is issued on an interconnect. Following, in response to the load instruction and while the barrier operation is pending, a load request is issued to memory. When a pre-determined type of invalidate, which is affiliated with the load request, is received before the receipt of an acknowledgment for the barrier operation, data that is returned by memory in response to the load request is discarded and the load request is re-issued. The pre-determined type of invalidate includes, for example, a snoop invalidate.
摘要翻译：公开了一种操作处理器的方法，通过该方法，回收了推测性发出的载入请求，其提取不正确的数据。接收指令序列，其中包括按程序顺序跟随障碍指令的障碍指令和加载指令，以执行。响应于屏障指令，在互连上发出屏障操作。接下来，响应于加载指令，并且当屏障操作正在等待时，向存储器发出加载请求。当在接收到屏障操作的确认之前接收到与加载请求相关联的预定类型的无效时，丢弃由存储器响应于加载请求而返回的数据，并且重新加载请求 -发行。预定类型的无效包括例如窥探无效。

92. 发明授权

US06349367B1 Method and system for communication in which a castout operation is cancelled in response to snoop responses 失效
标题翻译：用于通信的方法和系统，其中响应于窥探响应取消了退出操作
公开(公告)号：US06349367B1
公开(公告)日：2002-02-19
申请号：US09368228
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0804
摘要： An effectively “conditional”, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.
摘要翻译：可以通过对操作的组合的响应来取消有效的“有条件”，丢弃包括相关数据访问在内的组合操作的部分。组合的响应逻辑在窥探者和垂直的在线存储器中接收对应于被丢弃的受害者的高速缓存行的相关性状态和/或LRU位置信息。组合的响应逻辑还可以接收关于在受害者的同余类中的窥探者或低级存储器中存在共享或无效高速缓存行的信息，或者关于数据访问目标的一次读取性质的信息。基于这些响应，组合的响应逻辑确定是否应该取消推出，如果是，则选择并驱动适当的组合响应代码。

93. 发明授权

US06279086B1 Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position 失效
标题翻译：具有组合侦听响应的多处理器系统总线隐式更新snooper LRU位置
公开(公告)号：US06279086B1
公开(公告)日：2001-08-21
申请号：US09368227
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/123
摘要： Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines, from LRU position information appended to the combined response to the combined operation, whether the coherency state and/or LRU position of the victim may be upgraded within the subject storage device. If so, the coherency state or LRU position is upgraded to improve global data storage management. For instance, a cache line within a snooping storage device may be altered to assume the coherency state of the victim within the storage device initiating the combined operation to improve data storage management under a given replacement policy.
摘要翻译：在窥探组合的数据访问并且通过水平存储设备推出/取消分配操作时，窥探逻辑从附加到对组合操作的组合响应的LRU位置信息确定受害者的相关性状态和/或LRU位置是否可以在主题存储设备内进行升级。如果是这样，则一致性状态或LRU位置被升级以改进全局数据存储管理。例如，可以改变窥探存储设备内的高速缓存行，以假定存储设备内的受害者的一致性状态发起组合操作，以改善给定替换策略下的数据存储管理。

94. 发明授权

US06275909B1 Multiprocessor system bus with system controller explicitly updating snooper cache state information 失效
标题翻译：具有系统控制器的多处理器系统总线显式更新窥探缓存状态信息
公开(公告)号：US06275909B1
公开(公告)日：2001-08-14
申请号：US09368226
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831 , G06F12/0811
摘要： Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy with a coherency state of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state information appended to the combined operation and the snoop responses, whether a coherency upgrade is possible. If so, the combined response logic selects a snooper storage device to upgrade the coherency state of a respective cache line corresponding to the victim, and appends an upgrade directive to the combined response. The snooper selected to upgrade the coherency state of a cache line corresponding the victim may be randomly chosen or, as an optimization, be chosen for having the highest LRU position for the respective cache line.
摘要翻译：总线的组合响应逻辑接收组合的数据访问，并且通过存储分层结构的特定级别中的存储设备发起/撤销分配操作，所述存储层级具有附加的转出/取消分配的受害者的一致性状态。总线驱动器侦听器上的侦听器响应于与所附加的受害者对应的本地存储的缓存线的相关性状态和/或LRU位置的组合操作。组合响应逻辑从附加到组合操作和窥探响应的一致性状态信息确定是否可以进行一致性升级。如果是这样，组合的响应逻辑选择窥探存储设备来升级与受害者相对应的相应高速缓存行的一致性状态，并且将升级指令附加到组合响应。选择用于升级与受害者相对应的高速缓存线的相关性状态的窥探者可以被随机选择，或者作为优化被选择以具有用于相应高速缓存行的最高LRU位置。

95. 发明授权

US06880073B2 Speculative execution of instructions and processes before completion of preceding barrier operations 失效
标题翻译：完成前面的障碍操作之前，对指令和过程的推测执行
公开(公告)号：US06880073B2
公开(公告)日：2005-04-12
申请号：US09753053
申请日：2000-12-28
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Derek Edward Williams
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued prior to the return of the sync acknowledgment. Data returned is immediately forwarded to the processor's execution units. The returned data and results of subsequent operations are held temporarily in rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative. When a barrier acknowledge is received by the BOP controller, the flag(s) of the corresponding rename register(s) are reset.
摘要翻译：描述了提供完整的多处理器推测的数据处理系统和处理器，在系统总线上的屏障操作完成之前，推测性地执行指令序列中的屏障操作之后的所有指令。处理器包括具有屏障操作（BOP）控制器的加载/存储单元（LSU），其允许在指令序列中的同步之后的加载指令在返回同步确认之前被推测地发出。返回的数据立即转发到处理器的执行单元。返回的数据和后续操作的结果暂时保存在重命名寄存器中。在相应的重命名寄存器中设置多处理器推测标志，以指示该值为“屏障”推测。当BOP控制器接收到屏障确认时，相应的重命名寄存器的标志被重置。

96. 发明授权

US06801984B2 Imprecise snooping based invalidation mechanism 失效
标题翻译：不精确的基于窥探的无效机制
公开(公告)号：US06801984B2
公开(公告)日：2004-10-05
申请号：US09895119
申请日：2001-06-29
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The directional bits provide information that includes a processor cache identification (ID) and routing method. The processor cache ID indicates which processor's operation resulted in the cache line of the local processor changing to the invalidate (I) coherency state. The routing method indicates what transmission method to utilize to forward the cache line, from among a local system bus or a switch or broadcast mechanism. Processor/Cache directory logic provide responses to requests depending on the values of the directional bits.
摘要翻译：一种方法，系统和处理器高速缓存配置，其能够响应于在本地处理器高速缓存处的无效高速缓存未命中而有效地检索有效数据。除了一致性状态位和地址标签之外，向缓存目录提供一组方向位。方向位提供包括处理器缓存标识（ID）和路由方法的信息。处理器缓存ID指示哪个处理器的操作导致本地处理器的高速缓存行变为无效（I）一致性状态。该路由方法指示用于从本地系统总线或交换机或广播机制中转发高速缓存行的什么传输方法。处理器/缓存目录逻辑根据定向位的值提供对请求的响应。

97. 发明授权

US06728873B1 System and method for providing multiprocessor speculation within a speculative branch path 失效
标题翻译：在推测性分支路径中提供多处理器推测的系统和方法
公开(公告)号：US06728873B1
公开(公告)日：2004-04-27
申请号：US09588507
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842
摘要： Disclosed is a method of operation within a processor, that enhances speculative branch processing. A speculative execution path contains an instruction sequence that includes a barrier instruction followed by a load instruction. While a barrier operation associated with the barrier instruction is pending, a load request associated with the load instruction is speculatively issued to memory. A flag is set for the load request when it is speculatively issued and reset when an acknowledgment is received for the barrier operation. Data which is returned by the speculatively issued load request is temporarily held and forwarded to a register or execution unit of the data processing system after the acknowledgment is received. All process results, including data returned by the speculatively issued load instructions are discarded when the speculative execution path is determined to be incorrect.
摘要翻译：公开了一种处理器内的操作方法，其增强了推测性分支处理。推测执行路径包含指令序列，其中包含跟随加载指令的障碍指令。当与障碍指令相关联的障碍操作正在等待时，与加载指令相关联的加载请求被推测地发布到存储器。当推测性地发出加载请求时设置标志，并且当接收到用于屏障操作的确认时，重置该标志。在接收到确认之后，由推测发出的加载请求返回的数据被暂时保存并转发到数据处理系统的寄存器或执行单元。当推测性执行路径被确定为不正确时，所有处理结果（包括由推测发出的加载指令返回的数据）被丢弃。

98. 发明授权

US06725340B1 Mechanism for folding storage barrier operations in a multiprocessor system 失效
标题翻译：在多处理器系统中折叠存储屏障操作的机制
公开(公告)号：US06725340B1
公开(公告)日：2004-04-20
申请号：US09588509
申请日：2000-06-06
申请人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
发明人： Guy Lynn Guthrie , Ravi Kumar Arimilli , John Steven Dodson , Derek Edward Williams
IPC分类号： G06F9312
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859
摘要： Disclosed is a processor that reduces barrier operations during instruction processing. An instruction sequence includes a first barrier instruction and a second barrier instruction with a store instruction in between the first and second barrier instructions. A store request associated with the store instruction is issued prior to a barrier operation associated with the first barrier instruction. A determination is made of when the store request completes before the first barrier instruction has issued. In response, only a single barrier operation is issued for both the first and second barrier instructions. The single barrier operation is issued after the store request has been issued and at the time the second barrier operation is scheduled to be issued.
摘要翻译：公开了一种在指令处理期间减少屏障操作的处理器。指令序列包括在第一和第二屏障指令之间具有存储指令的第一屏障指令和第二屏障指令。在与第一屏障指令相关联的屏障操作之前发出与存储指令相关联的存储请求。确定存储请求何时在第一个屏障指令发出之前完成。作为响应，仅为第一和第二屏障指令发出单个屏障操作。单个屏障操作在存储请求已经被发出之后并且在第二屏障操作被安排发布的时候发出。

99. 发明授权

US06484241B2 Multiprocessor computer system with sectored cache line system bus protocol mechanism 失效
标题翻译：多处理器计算机系统采用高速缓存线路系统总线协议机制
公开(公告)号：US06484241B2
公开(公告)日：2002-11-19
申请号：US09752862
申请日：2000-12-28
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.
摘要翻译：一种在多处理器计算机系统中维持一致性的方法，其中每个处理单元的高速缓冲存储器具有高速缓存行。第一高速缓存一致性状态被分配给特定高速缓存行的一个扇区，并且与第一高速缓存一致性状态不同的第二高速缓存一致性状态被分配给总高速缓存行，同时保持第一高速缓存一致性状态部门。第一高速缓存一致性状态可以提供第一扇区包含不与任何其它高速缓存共享的有效值（即，排他或修改状态）的指示，并且第二高速缓存一致性状态可以提供以下指示：高速缓存行中的扇区包含与至少一个其他高速缓存（共享，最近读取或标记状态）共享的有效值。其他一致性状态可以应用于同一高速缓存行中的其他扇区。部分干预可以通过发出检索整个高速缓存线的请求来实现，并且仅响应于该请求仅提供高速缓存行的第一扇区。相同高速缓存行的第二扇区可以来自第三高速缓存。其他扇区也可以来自计算机系统的系统存储器设备。利用适当的系统总线代码将高速缓存操作发送到系统总线，并指示高速缓存行的哪些扇区是高速缓存操作的目标。

100. 发明授权

US06353875B1 Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions 失效
标题翻译：升级具有读/转发（RCO）地址事务的系统总线的窥探缓存状态机制
公开(公告)号：US06353875B1
公开(公告)日：2002-03-05
申请号：US09368223
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0831
摘要： Upon snooping a combined data access and castout/deallocate operation initiating by a horizontal storage device, snoop logic determines, from coherency state information appended to either the combined operation or the combined response to the operation, whether the coherency state of the victim may be upgraded within the subject storage device. If so, the coherency state is upgraded to improve global data storage management. For instance, a cache line may be upgraded from the shared coherency state to the exclusive coherency state to improve data storage management under a given replacement policy.
摘要翻译：在窥探由水平存储设备启动的组合数据访问和转发/释放操作时，窥探逻辑从附加到组合操作或对操作的组合响应的一致性状态信息确定是否可以升级受害者的一致性状态在主题存储设备内。如果是这样，则一致性状态被升级以改进全局数据存储管理。例如，高速缓存行可以从共享一致性状态升级到独占一致性状态，以改善给定替换策略下的数据存储管理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式