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91. 发明授权

US07145816B2 Using redundant memory for extra features 有权
公开(公告)号：US07145816B2
公开(公告)日：2006-12-05
申请号：US10918894
申请日：2004-08-16
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C8/12 , G11C16/0483 , G11C29/789
摘要： Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory array and is coupled to receive a command signal. The redundancy circuit is adapted to be selectively programmed for selecting a redundant portion of the memory array for programming extra features in response to the command signal when the redundant memory portion is not used for replacing the primary portion.

92. 发明申请

US20060227612A1 Common wordline flash array architecture 有权
公开(公告)号：US20060227612A1
公开(公告)日：2006-10-12
申请号：US11448220
申请日：2006-06-07
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C8/14
摘要： The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantially the same potential as the wordline to avoid erase disturbances. During programming operations, the unselected p-wells are pulled high to avoid gate disturbances.

93. 发明授权

US07080275B2 Method and apparatus using parasitic capacitance for synchronizing signals a device 有权
标题翻译：使用寄生电容来同步信号的装置的方法和装置
公开(公告)号：US07080275B2
公开(公告)日：2006-07-18
申请号：US10216439
申请日：2002-08-12
申请人： Ebrahim Abedifard , Frankie Roohparvar , Dean Nobunaga
发明人： Ebrahim Abedifard , Frankie Roohparvar , Dean Nobunaga
IPC分类号： G06F1/12
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed for introducing delay. The parasitic delay enables the clock, address, and control lines to be synchronized, yet does not require introducing delay blocks and so the overall speed of the memory device is improved.
摘要翻译：公开了一种用于补偿地址和控制线以解决存储器件内的时钟延迟的方法和装置。锁存器直接位于存储器件的存储区域内，使得地址和控制线内固有的寄生电容可以有利地用于引入延迟。寄生延迟使得时钟，地址和控制线能够同步，但不需要引入延迟块，因此提高了存储器件的整体速度。

94. 发明申请

US20060140042A1 High speed wordline decoder for driving a long wordline 有权
公开(公告)号：US20060140042A1
公开(公告)日：2006-06-29
申请号：US11288428
申请日：2005-11-29
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the wordline. Additionally, a voltage pump can supply operating voltage to the inverter to assist in overdriving the wordline. A voltage sink can also be coupled to the inverter which, in combination with the voltage pump, can be used to shift the output voltages used to turn the wordline on and off. A second inverter can also be added, and in such a case the transistors within the latch and the first inverter can be reduced in size, switching time, and power consumption.

95. 发明授权

US06949791B2 Flash cell with trench source-line connection 失效
标题翻译：具有沟槽源极线连接的闪存单元
公开(公告)号：US06949791B2
公开(公告)日：2005-09-27
申请号：US10848923
申请日：2004-05-19
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L31/062
CPC分类号： H01L27/11521 , H01L27/115
摘要： Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.
摘要翻译：具有沟槽源极线接触的浮栅存储器单元适合于增加的封装密度，而不需要以规则间隔放置在存储器阵列上的低电阻接地带。这种浮栅存储单元的漏区和源区形成在具有第一导电类型的第一半导体区中。该第一半导体区域通过具有不同于第一导电类型的第二导电类型的插入的第二半导体区域与下面的衬底分离。存储器单元的源极区域作为公共源极线耦合到第二半导体区域。可以通过向其控制栅极，漏极区域，第一半导体区域和第二半导体区域施加各种电位电平来对这样的存储单元进行编程，读取和擦除。

96. 发明申请

US20050024937A1 High speed low voltage driver 失效
公开(公告)号：US20050024937A1
公开(公告)日：2005-02-03
申请号：US10932413
申请日：2004-09-02
申请人： Ebrahim Abedifard , Frankie Roohparvar
发明人： Ebrahim Abedifard , Frankie Roohparvar
IPC分类号： G11C16/24 , G11C16/26 , G11C16/04
CPC分类号： G11C5/145 , G11C16/12 , G11C16/24 , G11C16/26
摘要： A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has risen substantially to a supply voltage without draining the pumped voltage.

97. 发明授权

US06711056B2 Memory with row redundancy 有权
公开(公告)号：US06711056B2
公开(公告)日：2004-03-23
申请号：US10199728
申请日：2002-07-19
申请人： Ebrahim Abedifard , Frankie Fariborz Roohparvar
发明人： Ebrahim Abedifard , Frankie Fariborz Roohparvar
IPC分类号： G11C1606
CPC分类号： G11C29/70
摘要： A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together or at a second level when four rows of the memory array are shorted together. The control circuitry instructs an address counter, during an erase operation, to increment row addresses of the rows of the memory array by two rows when the bit is at the first level or four rows when the bit is at the second level.

98. 发明授权

US06671214B2 Methods of operating a multiple bit line column redundancy scheme having primary and redundant local and global bit lines 有权
标题翻译：操作具有主和冗余局部和全局位线的多位线列冗余方案的方法
公开(公告)号：US06671214B2
公开(公告)日：2003-12-30
申请号：US10268353
申请日：2002-10-10
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C2900
CPC分类号： G11C29/82
摘要： Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.
摘要翻译：具有多个位线列冗余的存储器件适用于高性能存储器件，特别是参考同步非易失性存储器件。这样的存储器件包括以每列存储器单元耦合到局部位线的列排列的存储单元块。这种存储器件还包括具有选择性地耦合到每个全局位线的多个局部位线的全局位线，其中每个全局位线延伸到存储器扇区的每个存储器块中的本地位线。通过提供具有冗余读出放大器，全局位线和局部位线的存储器单元的冗余分组来实现扇区内的一个或多个存储单元的缺陷列的修复。每组记忆体单元包含四列或更多列的存储单元。一列存储器单元中的缺陷导致四列或更多列存储器单元的替换。

99. 发明授权

US06665221B2 Multiple bit line column redundancy with primary local and global bit lines and redundant local and global bit lines 有权
标题翻译：具有主局部和全局位线以及冗余局部和全局位线的多位线列冗余
公开(公告)号：US06665221B2
公开(公告)日：2003-12-16
申请号：US10268715
申请日：2002-10-10
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C2900
CPC分类号： G11C29/82
摘要： Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.
摘要翻译：具有多个位线列冗余的存储器件适用于高性能存储器件，特别是参考同步非易失性存储器件。这样的存储器件包括以每列存储器单元耦合到局部位线的列排列的存储单元块。这种存储器件还包括具有选择性地耦合到每个全局位线的多个局部位线的全局位线，其中每个全局位线延伸到存储器扇区的每个存储器块中的本地位线。通过提供具有冗余读出放大器，全局位线和局部位线的存储器单元的冗余分组来实现扇区内的一个或多个存储单元的缺陷列的修复。每组记忆体单元包含四列或更多列的存储单元。一列存储器单元中的缺陷导致四列或更多列存储器单元的替换。

100. 发明授权

US06560150B2 Memory device testing 有权
公开(公告)号：US06560150B2
公开(公告)日：2003-05-06
申请号：US10192328
申请日：2002-07-10
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/842
摘要： Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory device.

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