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91. 发明授权

US08549267B2 Methods and apparatus to manage partial-commit checkpoints with fixup support 有权
标题翻译：使用fixup支持来管理部分提交检查点的方法和设备
公开(公告)号：US08549267B2
公开(公告)日：2013-10-01
申请号：US12644151
申请日：2009-12-22
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.
摘要翻译：公开了用于管理部分提交检查点的示例性方法和装置。所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

92. 发明申请

US20120260072A1 REGISTER ALLOCATION IN ROTATION BASED ALIAS PROTECTION REGISTER 有权
标题翻译：基于旋转的ALIAS保护寄存器中的注册分配
公开(公告)号：US20120260072A1
公开(公告)日：2012-10-11
申请号：US13082146
申请日：2011-04-07
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3838 , G06F9/384
摘要： A system may comprises an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking constraint for the set of scheduled instructions, and allocate alias registers for the set of scheduled instructions based on the data dependence, the checking constraint and/or the anti-checking constraint. In one embodiment, the optimizer is to release unused registers to reduce the alias registers used to protect the scheduled instructions. The optimizer is further to insert a dummy instruction after a fused instruction to break cycles in the checking and anti-checking constraints.
摘要翻译：系统可以包括优化器/调度器，以在一组指令上调度，计算数据依赖性，检查约束和/或针对所设置的指令集合的反检查约束，并且为该组调度指令分配别名寄存器关于数据依赖性，检查约束和/或反检查约束。在一个实施例中，优化器是释放未使用的寄存器以减少用于保护调度指令的别名寄存器。优化器进一步在融合指令之后插入一个虚拟指令，以便在检查和反查约束中打破周期。

93. 发明申请

US20120054449A1 METHOD AND APPARATUS FOR FUZZY STRIDE PREFETCH 有权
标题翻译： FUZZY STRIDE PREFETCH的方法和装置
公开(公告)号：US20120054449A1
公开(公告)日：2012-03-01
申请号：US12871164
申请日：2010-08-30
申请人： Shiliang Hu , Youfeng Wu
发明人： Shiliang Hu , Youfeng Wu
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/1041 , G06F2212/502 , G06F2212/6024 , G06F2212/6026
摘要： In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一种预取引擎，用于检测存储器中的数据访问步进何时落入一个范围内，以计算预测的下一步，以使用预测的下一步来选择性地预取高速缓存行，并且动态地控制预取。还描述和要求保护其他实施例。

94. 发明申请

US20120016853A1 EFFICIENT AND CONSISTENT SOFTWARE TRANSACTIONAL MEMORY 有权
标题翻译：有效和一致的软件交易记忆
公开(公告)号：US20120016853A1
公开(公告)日：2012-01-19
申请号：US13246678
申请日：2011-09-27
申请人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
发明人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
IPC分类号： G06F7/00
CPC分类号： G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
摘要翻译：这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。此外，使用全局时间戳（GTS）来跟踪最近提交的事务。每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。待处理的交易将比较其在LTS阅读障碍中确定的版本。如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

95. 发明申请

US20110320781A1 DYNAMIC DATA SYNCHRONIZATION IN THREAD-LEVEL SPECULATION 审中-公开
标题翻译：动态数据同步在线程分析
公开(公告)号：US20110320781A1
公开(公告)日：2011-12-29
申请号：US12826287
申请日：2010-06-29
申请人： Wei Liu , Youfeng Wu
发明人： Wei Liu , Youfeng Wu
IPC分类号： G06F9/312 , G06F12/02 , G06F12/08
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851 , G06F9/52
摘要： In one embodiment, the present invention introduces a speculation engine to parallelize serial instructions by creating separate threads from the serial instructions and inserting processor instructions to set a synchronization bit before a dependence source and to clear the synchronization bit after a dependence source, where the synchronization bit is designed to stall a dependence sink from a thread running on a separate core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明引入了一种推测引擎，以通过从串行指令中创建单独的线程并插入处理器指令来在依赖源之前设置同步位并在依赖源之后清除同步位，从而并行化串行指令，其中同步位被设计为从在单独核心上运行的线程停止依赖宿。描述和要求保护其他实施例。

96. 发明授权

US07802136B2 Compiler technique for efficient register checkpointing to support transaction roll-back 有权
标题翻译：编译器技术，用于高效的注册检查点支持事务回滚
公开(公告)号：US07802136B2
公开(公告)日：2010-09-21
申请号：US11648486
申请日：2006-12-28
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F11/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/3834 , G06F11/1407
摘要： A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restore the live-in registers from the backup storage elements in response to an abort of the transaction.
摘要翻译：这里描述用于有效的寄存器检查点的方法和装置。在程序代码中检测到事务。在程序代码中插入恢复块，以响应于第一个事务的中止来执行恢复操作。回退边缘可能从中止点插入到恢复块。将控制流程边缘从恢复块插入到事务的入口点。检查点代码被插入到备份存储元件中的备份实时寄存器的入口点之前，并且恢复代码被插入到恢复块中，以便响应于事务的中止从备份存储元件恢复实时寄存器。

97. 发明申请

US20090172644A1 SOFTWARE FLOW TRACKING USING MULTIPLE THREADS 有权
标题翻译：使用多个线程的软件流程跟踪
公开(公告)号：US20090172644A1
公开(公告)日：2009-07-02
申请号：US11965271
申请日：2007-12-27
申请人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
发明人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
IPC分类号： G06F9/44
CPC分类号： G06F21/566 , G06F8/33 , G06F11/3636
摘要： Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.
摘要翻译：公开了用于执行动态信息流跟踪的方法，系统和机器可读介质。一种方法包括执行具有主线程的程序的操作，并且使用跟踪线程跟踪主线程对程序的操作的执行。该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值，以反映该值是否被污染，并且基于该着色值确定跟踪线程是否使用该值主线程违反了特定的安全策略。

98. 发明授权

US07506217B2 Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability 有权
标题翻译：用于软件错误检测的软件控制流程检查的装置和方法，以提高微处理器的可靠性
公开(公告)号：US07506217B2
公开(公告)日：2009-03-17
申请号：US11325773
申请日：2005-12-30
申请人： Edson Borin , Cheng C. Wang , Youfeng Wu
发明人： Edson Borin , Cheng C. Wang , Youfeng Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.
摘要翻译：一种用于软错误检测的基于软件的控制流程检查的方法和装置。在一个实施例中，该方法包括在基本块的结尾处对目标程序的一个基本块的仪表进行更新具有后继基本块签名的签名寄存器。另外，基本块被验证以验证签名寄存器的内容是否与基本块开头的基本块签名相匹配。在一个实施例中，如果签名寄存器的内容与基本块签名匹配，则在基本块内插入指令以使签名寄存器存储预定值。在一个实施例中，基本块可以被细分为多个区域; 每个区域都被分配一个签名，并在每个区域的开头进行检测以更新签名寄存器。描述和要求保护其他实施例。

99. 发明授权

US07467377B2 Methods and apparatus for compiler managed first cache bypassing 有权
标题翻译：编译器管理的第一个缓存绕过的方法和设备
公开(公告)号：US07467377B2
公开(公告)日：2008-12-16
申请号：US10278682
申请日：2002-10-22
申请人： Youfeng Wu , Li-Ling Chen
发明人： Youfeng Wu , Li-Ling Chen
IPC分类号： G06F9/45 , G06F12/00
CPC分类号： G06F12/0888 , G06F8/4442 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F12/0897
摘要： Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.
摘要翻译：公开了管理第一高速缓存的旁路的方法和装置。在一种这样的方法中，识别具有大于或等于预定阈值的预期等待时间的加载指令。然后进行请求以将所识别的加载指令调度为具有预定的延迟。然后安排软件程序。然后将与预定软件程序中的加载指令相关联的实际延迟与预定延迟进行比较。如果实际延迟大于或等于预定延迟，则加载指令被标记为绕过第一高速缓存。

100. 发明申请

US20080244538A1 Multi-core processor virtualization based on dynamic binary translation 审中-公开
标题翻译：基于动态二进制翻译的多核处理器虚拟化
公开(公告)号：US20080244538A1
公开(公告)日：2008-10-02
申请号：US11728347
申请日：2007-03-26
申请人： Sreekumar R. Nair , Youfeng Wu
发明人： Sreekumar R. Nair , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F9/45554
摘要： A processor virtualization abstracts the behavior of a processor instruction set architecture from an underlying micro-architecture implementation. It is capable of running any processor instruction set architecture compatible software on any micro-architecture implementation. A system wide dynamic binary translator translates source system programs to target programs and manages the execution of those target programs. It also provides the necessary and sufficient infrastructure requires to render multi-core processor virtualization.
摘要翻译：处理器虚拟化从基础微架构实现中抽象出处理器指令集架构的行为。它能够在任何微架构实现上运行任何处理器指令集架构兼容的软件。系统的动态二进制翻译器将源系统程序转换为目标程序，并管理这些目标程序的执行。它还提供了必要和足够的基础架构来呈现多核处理器虚拟化。

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