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91. 发明申请

US20090101969A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090101969A1
公开(公告)日：2009-04-23
申请号：US12248577
申请日：2008-10-09
申请人： Ryota KATSUMATA , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Ryota KATSUMATA , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/0692 , H01L29/4238 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.
摘要翻译：一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

92. 发明申请

US20080315291A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080315291A1
公开(公告)日：2008-12-25
申请号：US12140734
申请日：2008-06-17
申请人： Masaru KITO , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
发明人： Masaru KITO , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L27/105 , H01L21/02161 , H01L21/02164 , H01L21/0217 , H01L21/31645 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.
摘要翻译：非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体，第一导体与第一块绝缘体相邻形成。

93. 发明申请

US20080180994A1 MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SAME 有权
标题翻译：存储器系统，半导体存储器件及其驱动方法
公开(公告)号：US20080180994A1
公开(公告)日：2008-07-31
申请号：US11955900
申请日：2007-12-13
申请人： Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Hideaki Aochi , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
发明人： Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Hideaki Aochi , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
IPC分类号： G11C11/34 , H01L29/76 , G11C8/00
CPC分类号： H01L27/115 , G11C7/18 , G11C8/08 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.
摘要翻译：半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管，垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅极和所述第二虚设晶体管的栅电极写入操作的时间将数据写入到所述存储单元晶体管。

94. 发明申请

US20070252201A1 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070252201A1
公开(公告)日：2007-11-01
申请号：US11654551
申请日：2007-01-18
申请人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L29/76
CPC分类号： H01L27/11582 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
摘要翻译：提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

95. 发明授权

US08350326B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08350326B2
公开(公告)日：2013-01-08
申请号：US12839895
申请日：2010-07-20
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/42344 , H01L29/66833
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构体，第一和第二半导体柱，存储单元连接部分，选择单元堆叠结构体，第一和第二选择单元半导体柱，选择单元连接部分，以及第一至第五互连。半导体支柱刺穿堆叠的结构体。第一和第二互连分别连接到第一和第二半导体柱。存储单元连接部连接第一和第二半导体柱。选择单元半导体柱刺穿选择单元堆叠结构体。第三和第四互连分别连接到第一和第二选择单元半导体柱。选择单元连接部分连接第一和第二选择单元半导体柱。第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。

96. 发明授权

US08154103B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08154103B2
公开(公告)日：2012-04-10
申请号：US12972243
申请日：2010-12-17
申请人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/0649 , H01L29/7923 , H01L29/7926
摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
摘要翻译：半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且漏极区域与主体部分连接。

97. 发明申请

US20110111579A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20110111579A1
公开(公告)日：2011-05-12
申请号：US13010466
申请日：2011-01-20
申请人： Masaru Kito , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Masaru Kito , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L21/20
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11573 , H01L27/11582 , H01L29/66833 , H01L29/7923 , H01L29/7926
摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.
摘要翻译：非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。每个存储器串包括：在垂直于衬底的方向上延伸的存储器柱状半导体; 与记录柱状半导体接触的隧道绝缘层; 与隧道绝缘层接触并积累电荷的电荷累积层; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个存储器导电层。电荷累积层的下部被隧道绝缘层和块绝缘层覆盖。

98. 发明授权

US07927926B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07927926B2
公开(公告)日：2011-04-19
申请号：US12908546
申请日：2010-10-20
申请人： Ryota Katsumata , Masaru Kito , Hiroyasu Tanaka , Masaru Kidoh , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Ryota Katsumata , Masaru Kito , Hiroyasu Tanaka , Masaru Kidoh , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L21/82
CPC分类号： H01L21/764 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578
摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.
摘要翻译：非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。每个存储器串包括：沿垂直方向延伸到衬底的第一柱状半导体层; 电荷累积层，经由第一绝缘层形成在第一柱状半导体层周围; 以及经由第二绝缘层形成在电荷累积层周围的第一导电层。每个第一导电层被形成为以二维方式膨胀，并且在位于其上方和下方的第一导电层之间形成气隙。

99. 发明申请

US20110084331A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110084331A1
公开(公告)日：2011-04-14
申请号：US12972243
申请日：2010-12-17
申请人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Yoshiaki Fukuzumi , Masaru Kito , Yasuyuki Matsuoka
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/0649 , H01L29/7923 , H01L29/7926
摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.
摘要翻译：半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且漏极区域与主体部分连接。

100. 发明授权

US07847342B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US07847342B2
公开(公告)日：2010-12-07
申请号：US12325023
申请日：2008-11-28
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L27/115 , H01L21/336 , H01L29/792 , H01L21/8247
CPC分类号： H01L27/11578 , G11C16/0483 , H01L21/8221 , H01L27/115 , H01L27/11556
摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells.
摘要翻译：非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。每个存储器串包括：第一柱状半导体层，其在垂直于衬底的方向上延伸并具有从其上端向下延伸的第一中空; 形成为与第一柱状半导体层的外壁接触的第一绝缘层; 第二绝缘层，形成在第一柱状半导体层的内壁上以离开第一中空部; 以及形成为将第一绝缘层与第一柱状半导体层夹在中间并用作存储单元的控制电极的多个第一导电层。

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