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91. 发明授权

US06349068B2 Semiconductor memory device capable of reducing power consumption in self-refresh operation 有权
标题翻译：能够降低自刷新操作中的功耗的半导体存储器件
公开(公告)号：US06349068B2
公开(公告)日：2002-02-19
申请号：US09828847
申请日：2001-04-10
申请人： Yoshihiro Takemae , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Yasurou Matsuzaki
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.
摘要翻译：刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

92. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

93. 发明授权

US5594699A DRAM with reduced electric power consumption 失效
标题翻译： DRAM具有降低的电力消耗
公开(公告)号：US5594699A
公开(公告)日：1997-01-14
申请号：US308105
申请日：1994-09-16
申请人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
发明人： Yukihiro Nomura , Yasuharu Satoh , Yoshihiro Takemae , Takaaki Furuyama , Mitsuhiro Nagao , Masahiro Niimi
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C5/143
摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.
摘要翻译：具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元，数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于第一电压电平。

94. 发明授权

US5557221A Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
标题翻译：具有适用于小振幅操作的输入/输出接口的半导体集成电路
公开(公告)号：US5557221A
公开(公告)日：1996-09-17
申请号：US76434
申请日：1993-06-14
申请人： Masao Taguchi , Satoshi Eto , Yoshihiro Takemae , Hiroshi Yoshioka , Makoto Koga
发明人： Masao Taguchi , Satoshi Eto , Yoshihiro Takemae , Hiroshi Yoshioka , Makoto Koga
IPC分类号： H03K19/0185 , H03F3/45
CPC分类号： H03K19/018585
摘要： A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
摘要翻译：半导体集成电路包括用于控制向接收输入信号的信号放大电路提供电源电压的开关单元，以及根据该开关单元的幅度或频率选择性地接通和断开开关单元的控制单元输入信号。通过该结构，可以提供能够应用于适于小振幅操作的输入/输出接口的输入电路或输出电路。

95. 发明授权

US5537354A Semiconductor memory device and method of forming the same 失效
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US5537354A
公开(公告)日：1996-07-16
申请号：US357307
申请日：1994-12-14
申请人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
发明人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
IPC分类号： G11C11/401 , F02B75/02 , G11C7/10 , G11C11/407 , G11C11/409 , G11C13/00
CPC分类号： G11C7/1072 , F02B2075/025
摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.
摘要翻译：将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

96. 发明授权

US5307316A Semiconductor memory unit having redundant structure 失效
标题翻译：具有冗余结构的半导体存储单元
公开(公告)号：US5307316A
公开(公告)日：1994-04-26
申请号：US861822
申请日：1992-06-16
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： H01L27/10 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/86 , G11C7/00
CPC分类号： G11C29/81 , G11C29/832
摘要： A semiconductor memory device has a plurality of main memory blocks formed on a chip and each having a redundancy, a sub-memory block formed on the chip and having a substantially identical construction as that of each main memory block, a defect address memory circuit for storing address data of the main memory block that cannot be saved by the redundancy, and a redundancy control circuit for selecting the sub-memory block when a defective main memory block is selected.
摘要翻译： PCT No.PCT / JP91 / 01406 Sec。 371日期：1992年6月16日 102（e）日期1992年6月16日PCT 1991年10月16日PCT公布。公开号WO92 / 07362 日期：1992年04月30日。半导体存储器件具有形成在芯片上并具有冗余的多个主存储器块，形成在芯片上的子存储块，并且具有与每个主存储器块相同的结构，用于存储不能由冗余保存的主存储块的地址数据的缺陷地址存储电路，以及当选择缺陷主存储块时用于选择子存储块的冗余控制电路。

97. 发明授权

US4982366A Static semiconductor memory with readout inhibit means 失效
标题翻译：具有读出禁止装置的静态半导体存储器
公开(公告)号：US4982366A
公开(公告)日：1991-01-01
申请号：US467348
申请日：1990-01-22
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G11C11/413 , G06F11/16 , G11C8/20 , G11C11/409 , G11C11/418 , G11C29/00 , G11C29/04 , H01L27/10
CPC分类号： G11C8/20 , G05B2219/25381
摘要： A static semiconductor memory device includes a memory cell array including a large number of static memory cells arranged in a matrix fashion, a word decoder, a column decoder, and a data buffer. An address delay buffer is provided for delaying an input address signal by a predetermined delay time and a comparator circuit is provided for comparing the input address signal with the delayed address signal from the address delay buffer, so that even if the input address signal is disturbed by noise, the erroneous data corresponding to the disturbed address signal is not read into the data buffer by means of the output signal of the comparator circuit and is not output from the memory device.
摘要翻译：静态半导体存储器件包括存储单元阵列，其包括以矩阵方式布置的大量静态存储器单元，字解码器，列解码器和数据缓冲器。提供地址延迟缓冲器用于将输入地址信号延迟预定的延迟时间，并且提供比较器电路用于将输入地址信号与来自地址延迟缓冲器的延迟地址信号进行比较，使得即使输入地址信号被干扰通过噪声，与干扰的地址信号相对应的错误数据不通过比较器电路的输出信号被读入数据缓冲器，并且不从存储器件输出。

98. 发明授权

US4970693A Semiconductor memory device with internal control signal based upon output timing 失效
标题翻译：具有基于输出定时的内部控制信号的半导体存储器件
公开(公告)号：US4970693A
公开(公告)日：1990-11-13
申请号：US484474
申请日：1990-02-23
申请人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
发明人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C11/409 , G11C7/22 , G11C8/18 , G11C11/40 , G11C11/413
CPC分类号： G11C7/22 , G11C8/18
摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.
摘要翻译：半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。输出电路具有连接到参考电位线的外部输出端子。输出电路用于产生到外部输出端子的输出。禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

99. 发明授权

US4879685A Semiconductor memory device with internal array transfer capability 失效
标题翻译：具有内部阵列传输能力的半导体存储器件
公开(公告)号：US4879685A
公开(公告)日：1989-11-07
申请号：US311367
申请日：1989-02-16
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G11C7/00 , G11C8/04 , G11C11/401 , H01L27/10
CPC分类号： G11C7/00 , G11C8/04
摘要： A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.
摘要翻译：半导体存储器件包括多个字线，多个位线和多个存储单元，每个位线和字线连接在字线和位线之间的字线和位线的每个交叉处。每个连接到每对位线的多个读出放大器用于放大每个位线之间的电位差; 多个位线复位电路，每个连接到每对位线，在读/写周期期间电位差被保持。传输模式设置电路用于可选地选择第一字线，然后选择第二字线，并且用于同时将连接到第一字线的每个存储单元中的数据读出到每个位线上，然后同时在每个位线上写入数据由读出放大器放大成连接到第二字线的每个对应的存储单元。

100. 发明授权

US4807193A Semiconductor memory device with a detection circuit to detect word line potential 失效
标题翻译：具有检测电路的半导体存储器件，用于检测字线电位
公开(公告)号：US4807193A
公开(公告)日：1989-02-21
申请号：US81559
申请日：1987-02-25
申请人： Yoshihiro Takemae , Takeo Takematsu , Kimiaki Sato , Takashi Horii , Nobumi Kodama , Makoto Yanagisawa , Yasuhiro Takada
发明人： Yoshihiro Takemae , Takeo Takematsu , Kimiaki Sato , Takashi Horii , Nobumi Kodama , Makoto Yanagisawa , Yasuhiro Takada
IPC分类号： G11C11/409 , G11C7/22 , G11C8/18 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C7/22
摘要： A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.
摘要翻译：具有用于检测字线的电位的检测电路的单晶体管单电容型半导体存储器件，以确定用于驱动读出放大器的适当定时，从而提高存储器操作的速度。

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