专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US6107129A Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance 失效
标题翻译：具有多个LDD和/或源极/漏极注入步骤以增强电路性能的集成电路
公开(公告)号：US6107129A
公开(公告)日：2000-08-22
申请号：US38511
申请日：1998-03-11
申请人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , Fred N. Hause , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/6659 , H01L29/7833 , H01L29/7835
摘要： An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
摘要翻译：形成集成电路，由此产生提高集成电路总体速度的MOS晶体管结。晶体管结包括多个注入到结点的轻掺杂漏极（LDD）区域，结点的源极/漏极区域以及LDD和源极/漏极区域两者。多个植入物的第一植入物用于调节植入区域，使得第二和随后的植入物以相对高的浓度精确地放置在基底表面附近。因此，所得到的结是具有相对高的驱动强度，低接触电阻率，低的源到漏寄生电阻和相对低的结电容的结。

92. 发明授权

US6091105A Method of making a self-aligned dopant enhanced RTA MOSFET 失效
标题翻译：制造自对准掺杂剂RTA MOSFET的方法
公开(公告)号：US6091105A
公开(公告)日：2000-07-18
申请号：US50753
申请日：1998-03-30
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/336 , H01L29/78 , H01L29/72
CPC分类号： H01L29/66666 , H01L29/7827
摘要： An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.
摘要翻译：提供一种集成电路及其制造方法。在衬底中形成沟槽。沟槽有侧壁。在侧壁上形成第一绝缘层。在第一绝缘层上形成栅电极。在衬底中形成第一源极/漏极区域，并且在衬底中形成第二源极/漏极区域。第一源极/漏极区域的第一部分和第二源极/漏极区域的第二部分垂直间隔开以限定衬底中的沟道区域。该过程使得通道长度被设置为独立于用于图案化晶片的光刻系统的最大分辨率。可以实现非常短的通道长度。

93. 发明授权

US6060369A Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET 失效
标题翻译：含氮牺牲氧化物，具有高性能MOSFET的高氮掺杂剂分布
公开(公告)号：US6060369A
公开(公告)日：2000-05-09
申请号：US997318
申请日：1997-12-23
申请人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
发明人： Mark I. Gardner , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807
摘要： A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.
摘要翻译：提供在通道区域中具有高氮浓度的集成电路晶体管及其制造方法。在基材上生长与含氮物质结合的牺牲氧化物层。含氮物质的一部分扩散到衬底中以形成氮掺杂区域。通过第一氧化物层注入氮气以增加氮掺杂区域中氮的峰值浓度。去除牺牲氧化物层并形成非常薄的栅极氧化物层。形成栅极，源极和漏极。结果是具有非常薄的栅极氧化物层和基本上在Si-SiO 2界面处的高的峰值浓度的集成电路晶体管。

94. 发明授权

US6057584A Semiconductor device having a tri-layer gate insulating dielectric 失效
标题翻译：具有三层栅极绝缘电介质的半导体器件
公开(公告)号：US6057584A
公开(公告)日：2000-05-02
申请号：US994302
申请日：1997-12-19
申请人： Mark I. Gardner , Mark C. Gilmer , H. Jim Fulford , Jack C. Lee
发明人： Mark I. Gardner , Mark C. Gilmer , H. Jim Fulford , Jack C. Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66583 , H01L21/2822 , H01L21/28229
摘要： A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.
摘要翻译：具有栅绝缘三层的半导体器件包括衬底，设置在衬底上的含氮层，设置在含氮层上的第一介电层，设置在第一介电层上的第二电介质层和栅电极设置在第二电介质层上。使用介电常数为4〜100的氧化物形成第一和第二电介质层中的一个，并且使用介电常数介于10〜10000的氧化物形成第一和第二电介质层中的另一个。

95. 发明授权

US6030752A Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device 失效
标题翻译：在制造半导体器件期间缝合由相邻图像图案定义的片段的方法
公开(公告)号：US6030752A
公开(公告)日：2000-02-29
申请号：US805534
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： G03F7/20
CPC分类号： G03F7/70475
摘要： A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image pattern over the substrate that defines a first segment and a contact region, projecting a second image pattern over the substrate that defines a second segment with an end that overlaps the contact region, and removing a portion of the material corresponding to the first and second image patterns to form the first and second segments stitched by a portion of the contact region. The contact region has a greater width than the first and second segments. In this manner, the contact region accommodates misalignments that might otherwise lead to inadequate coupling or decoupling between the first and second segments. The invention is particularly well-suited for stitching polysilicon gates of N-channel and P-channel devices.
摘要翻译：公开了一种在制造半导体器件期间缝合由光刻系统的相邻图像图案限定的片段的方法。该方法包括在半导体衬底上形成材料，将限定第一部分和接触区域的第一图案图案投影在衬底上，将限定第二部分的第二图像图案投影在衬底上，端部与接触区域重叠以及去除对应于第一和第二图像图案的材料的一部分以形成由接触区域的一部分缝合的第一和第二段。接触区域具有比第一和第二段更大的宽度。以这种方式，接触区域适应可能导致第一和第二段之间不充分的耦合或解耦的未对准。本发明特别适用于拼接N沟道和P沟道器件的多晶硅栅极。

96. 发明授权

US5976956A Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device 失效
标题翻译：在器件中栅极形成之前使用瞬态增强扩散来控制掺杂剂浓度的方法
公开(公告)号：US5976956A
公开(公告)日：1999-11-02
申请号：US837936
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/336 , H01L21/265 , H01L21/322 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/3221 , Y10S148/024 , Y10S148/06
摘要： Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attracting selected dopants that are trapped in the silicon substrate. Dopants are implanted in the vicinity of the damaged regions and diffused by transient-enhanced diffusion (TED) into the damaged regions by thermal cycling to accumulate dopant atoms. Transient-enhanced diffusion improves the doping of a substrate by enhancing the diffusion of dopants at relatively low anneal temperatures. Dopant accumulation sets particular selected electrical properties without placing an excessive amount of dopant in regions adjacent to junctions for purposes including threshold control for a field device, threshold setting for a transistor, and prevention of device punchthrough.
摘要翻译：掺杂原子具有由于植入物损伤而变化的扩散系数。通过在形成栅电极之前将硅原子注入到硅衬底中来选择并产生损伤区域。硅原子用作吸收被捕获在硅衬底中的所选掺杂剂的吸气剂。掺杂剂被注入到受损区域附近，并通过热循环通过瞬态增强扩散（TED）扩散到受损区域以积累掺杂剂原子。瞬态增强扩散通过在相对低的退火温度下增强掺杂剂的扩散来改善衬底的掺杂。掺杂剂累积设置特定选择的电性能，而不会在邻近接点的区域中放置过量的掺杂剂，包括用于现场设备的阈值控制，晶体管的阈值设置以及防止器件穿透。

97. 发明授权

US5930642A Transistor with buried insulative layer beneath the channel region 失效
标题翻译：晶体管与通道区域之下的埋入绝缘层
公开(公告)号：US5930642A
公开(公告)日：1999-07-27
申请号：US871468
申请日：1997-06-09
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L21/762 , H01L29/786 , H01L29/24
CPC分类号： H01L29/78696 , H01L21/26533 , H01L21/266 , H01L21/76243 , H01L29/6659 , H01L29/66772 , H01L29/78603 , H01L29/78654
摘要： A transistor with a buried insulative layer beneath a channel region is disclosed. Unlike conventional SIMOX, the buried insulative layer has a top surface beneath the channel region that is closer than bottom surfaces of the source and drain to the top surface of the substrate. Preferably, the buried insulative layer is formed by implanting oxygen into the substrate and then performing a high-temperature anneal so that the implanted oxygen reacts with silicon in the substrate to form a continuous stoichiometric layer of silicon dioxide. Advantageously, the buried insulative layer provides a diffusion barrier and an electrical isolation barrier for the channel region.
摘要翻译：公开了一种在沟道区下方具有埋入绝缘层的晶体管。与常规SIMOX不同，掩埋绝缘层在通道区域下方具有比源极和漏极的底表面更靠近衬底顶表面的顶表面。优选地，通过将氧注入到衬底中然后进行高温退火来形成掩埋绝缘层，使得注入的氧与衬底中的硅反应形成连续化学计量的二氧化硅层。有利地，掩埋绝缘层为通道区域提供扩散阻挡层和电隔离屏障。

98. 发明授权

US5923983A Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects 失效
标题翻译：集成电路栅极导体，其具有基本上抵抗热载流子效应的栅极电介质
公开(公告)号：US5923983A
公开(公告)日：1999-07-13
申请号：US771871
申请日：1996-12-23
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/28247 , H01L29/4983 , H01L29/6659
摘要： An integrated circuit is formed whereby transistor gate dielectrics are made less susceptible to hot carrier effects. Barrier atoms are inserted into critical areas to minimize trapping of hot carriers within the gate dielectric. Barrier atoms are incorporated into critical areas within the gate dielectric, primarily at the juncture between the gate dielectric and the overlying gate conductor and underlying substrate. The barrier atoms serve to eliminate bond opportunities of hot carriers injected from the drain area. The barrier atoms are presented by elevating the temperature of the integrated circuit being produced and the barrier-embodied gas surrounding the circuit. The elevated temperatures occur within either an RTA furnace or an oxidizing furnace. Significant is the incorporation of barrier atoms during a normal process flow, either during polysilicon oxidation and/or implant anneal. According to one embodiment, barrier atoms are incorporated after the LDD implant during times in which a polysilicon oxide is grown. According to a second embodiment, barrier atoms are incorporated after the source/drain implant and during anneal of those implant species. In yet another embodiment, barrier atoms are incorporated during each of the above steps.
摘要翻译：形成集成电路，由此使得晶体管栅极电介质不易受热载流子效应的影响。阻挡原子被插入关键区域以最小化栅极电介质中热载流子的捕获。栅极原子被并入到栅极电介质的关键区域中，主要在栅极电介质和上覆栅极导体和下面的衬底之间的接合处。势垒原子用于消除从漏极区域注入的热载流子的键合机会。通过提高所产生的集成电路的温度和围绕电路的屏障实施的气体来呈现阻挡原子。高温发生在RTA炉或氧化炉内。重要的是在正常工艺流程期间，在多晶硅氧化和/或注入退火期间引入势垒原子。根据一个实施方案，在生长多晶氧化物的时间内，在LDD注入之后结合势垒原子。根据第二实施例，在源极/漏极注入之后并且在那些植入物种的退火期间并入势垒原子。在另一个实施方案中，在上述每个步骤期间并入阻挡原子。

99. 发明授权

US5899732A Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device 失效
标题翻译：通过多晶硅栅极注入硅的方法，用于半导体器件的穿通控制
公开(公告)号：US5899732A
公开(公告)日：1999-05-04
申请号：US837937
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/225 , H01L21/265 , H01L21/322 , H01L21/336 , H01L21/8238 , H01L29/10
CPC分类号： H01L29/66492 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/8238 , H01L29/1083 , H01L29/6659
摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.
摘要翻译：受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。先前损坏的区域位于确定设备穿透特性的位置。用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

100. 发明授权

US5888675A Reticle that compensates for radiation-induced lens error in a photolithographic system 失效
标题翻译：补偿光刻系统中辐射诱发的透镜误差的光罩
公开(公告)号：US5888675A
公开(公告)日：1999-03-30
申请号：US760031
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F1/00 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式