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91. 发明授权

US07489204B2 Method and structure for chip-level testing of wire delay independent of silicon delay 失效
标题翻译：线延迟芯片级测试的方法和结构独立于硅延迟
公开(公告)号：US07489204B2
公开(公告)日：2009-02-10
申请号：US11160603
申请日：2005-06-30
申请人： Peter A. Habitz , Anthony D. Polson
发明人： Peter A. Habitz , Anthony D. Polson
IPC分类号： G01R23/00 , H03B5/24 , H03K3/03
CPC分类号： G01R31/31725 , G01R31/3016
摘要： Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to either a first wire or a second wire by a multiplexer. A monitor measures ring frequencies of the ring oscillator when connected to either the first or second wire. A processor determines the wire delay based upon differences in the ring frequencies. Additional testers or multiple stages of a single tester may be embedded into either the same metal layer at a different location or into a different metal layer to allow for intra-metal layer or inter-metal layer comparisons of wire delay. Since metal capacitance and silicon load remains constant for both the first and second wires and the transient voltage change along the wire is hold small, metal delay is separable from delay due to silicon device performance. Pass/Fail criteria based upon a maximum allowable resistance-capacitance delay for a metal layer or based upon a comparison of resistance-capacitance delays across the same metal layer or between metal layers can be used to reject a chip.
摘要翻译：公开了用于在独立于硅延迟的芯片级测试位置特定的线延迟的方法和结构。本发明结合使用嵌入在芯片的金属层中的测试仪。测试器包括环形振荡器，其通过多路复用器选择性地连接到第一线或第二线。当连接到第一根或第二根导线时，监视器测量环形振荡器的振铃频率。处理器根据环频的差异来确定导线延迟。单个测试器的附加测试器或多个阶段可以嵌入到不同位置处的相同金属层中或者嵌入到不同的金属层中以允许金属间层或金属间层对比延迟线。由于金属电容和硅负载对于第一和第二导线都保持恒定，并且沿着导线的瞬态电压变化保持较小，所以由于硅器件性能，金属延迟与延迟分离。可以使用基于金属层的最大允许电阻 - 电容延迟或基于相同金属层或金属层之间的电阻 - 电容延迟的比较的通过/失败标准来拒绝芯片。

92. 发明授权

US07464359B2 Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure 失效
标题翻译：用于重新路由互连阵列以改善单个网络中的交换行为和相关联的互连阵列结构的方法
公开(公告)号：US07464359B2
公开(公告)日：2008-12-09
申请号：US11277541
申请日：2006-03-27
申请人： Peter A. Habitz , William J. Livingstone
发明人： Peter A. Habitz , William J. Livingstone
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array that incorporates identifying a victim net and at least two aggressor nets and crossing the aggressor nets so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net in order to minimizes the impact of coupling capacitance on the victim net with minimal changes to the wiring environment.
摘要翻译：公开了用于电路的互连阵列的实施例。互连阵列包括被平行于和相邻于多个交叉侵入网络的部分定位的受害网络，从而最小化电路由于耦合电容而导致的延迟或假开关的暴露。还公开了一种重新路由互连阵列的相关联的方法的实施例，该互连阵列包括识别受害网和至少两个攻击者网并且横穿攻击网，使得多个攻击者网的部分平行于并邻近受害网以便最小化耦合电容对受害网络的影响，同时对接线环境进行最小的改变。

93. 发明申请

US20080216036A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
公开(公告)号：US20080216036A1
公开(公告)日：2008-09-04
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

94. 发明申请

US20080209372A1 Estimation Of Process Variation Impact Of Slack In Multi-Corner Path-Based Static Timing Analysis 失效
标题翻译：基于多角度路径的静态时序分析中过程变化对松弛影响的估计
公开(公告)号：US20080209372A1
公开(公告)日：2008-08-28
申请号：US11679171
申请日：2007-02-26
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Jeffrey M. Ritzinger , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Jeffrey M. Ritzinger , Xiaoyue Wang
IPC分类号： G06F9/45
CPC分类号： G06F17/5031
摘要： A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path.
摘要翻译：一种用于在多角静态时序分析中减少要分析的路径的数量的方法和系统。基于用于赛车路径的非公共路径延迟的估计的上部松弛变化被用于确定是否可以绕过赛车路径绕过多角度静态时序分析。在另一示例中，基于用于赛车路径的总延迟的估计的最大RSS信用被用于确定是否可以绕过赛道路径绕过多角度静态时序分析。

95. 发明授权

US07089143B2 Method and system for evaluating timing in an integrated circuit 失效
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07089143B2
公开(公告)日：2006-08-08
申请号：US10709361
申请日：2004-04-29
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G01M19/00 , G06F9/45
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

96. 发明授权

US07089129B2 Electromigration check of signal nets using net capacitance to evaluate thermal characteristics 失效
标题翻译：使用净电容对信号网进行电迁移检查，以评估热特性
公开(公告)号：US07089129B2
公开(公告)日：2006-08-08
申请号：US10605990
申请日：2003-11-12
申请人： Peter A. Habitz
发明人： Peter A. Habitz
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A method for performing an electromigration check and detecting EM problems in a device or circuit. The method uses the capacitance and resistance of the conductors of the device or circuit as parameters in determining a power limit that maintains a required temperature environment that ensures the reliability of the device or circuit. The power limit is then used to check each device interconnect to identify the location of potential EM problems. Corrective action is taken to avoid EM problems as they are detected in the device or circuit.
摘要翻译：一种用于执行电迁移检查和检测装置或电路中的EM问题的方法。该方法使用器件或电路的导体的电容和电阻作为确定功率限制的参数，维持所需的温度环境，以确保器件或电路的可靠性。然后使用功率限制来检查每个设备互连以识别潜在EM问题的位置。采取纠正措施以避免在设备或电路中检测到EM问题。

97. 发明授权

US06948146B2 Simplified tiling pattern method 失效
标题翻译：简化的平铺图案法
公开(公告)号：US06948146B2
公开(公告)日：2005-09-20
申请号：US10248324
申请日：2003-01-09
申请人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William C. Leipold , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Peter A. Habitz , William C. Leipold , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： H01L23/528 , G06F17/5068 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a design and an integrated circuit having a substantially uniform density and electrical characteristics between parts of the IC that are angled at 45 degrees relative to one another. In particular, the invention provides fill tiling patterns oriented substantially uniformly to electrical structures of either orthogonal or 45 degree angle orientation.
摘要翻译：本发明提供了一种设计和集成电路，其具有在相对于彼此成45度成角度的IC的部分之间具有基本均匀的密度和电特性。特别地，本发明提供了基本上均匀地定向到正交或45度角取向的电结构的填充平铺图案。

98. 发明授权

US06490708B2 Method of integrated circuit design by selection of noise tolerant gates 失效
公开(公告)号：US06490708B2
公开(公告)日：2002-12-03
申请号：US09812211
申请日：2001-03-19
申请人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
发明人： John M. Cohn , Scott W. Gould , Peter A. Habitz , Jose L. P. Neves , William F. Smith , Larry Wissel , Paul S. Zuchowski
IPC分类号： G06E1750
CPC分类号： G06F17/505
摘要： A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

99. 发明授权

US5045911A Lateral PNP transistor and method for forming same 失效
标题翻译：横向PNP晶体管及其形成方法
公开(公告)号：US5045911A
公开(公告)日：1991-09-03
申请号：US608609
申请日：1990-10-30
申请人： Peter A. Habitz , Chang-Ming Hsieh , Yi-Shiou Huang
发明人： Peter A. Habitz , Chang-Ming Hsieh , Yi-Shiou Huang
IPC分类号： H01L21/331 , H01L21/761 , H01L29/10
CPC分类号： H01L29/6625 , H01L21/761 , H01L29/1008
摘要： A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.
摘要翻译：形成横向PNP晶体管的工艺包括以下步骤：提供包括隔离的N器件区域的半导体材料芯片; 以相对低功率和低剂量将N掺杂剂材料注入到所述器件区域的选定植入区域中; 以相对更高的功率和更高剂量将N掺杂剂材料注入植入区域; 以及在器件区域中形成发射极和集电极区域，使得在植入区域中的集电极和发射极区域之间限定本征基极区域。

100. 发明授权

US4996164A Method for forming lateral PNP transistor 失效
标题翻译：形成横向PNP晶体管的方法
公开(公告)号：US4996164A
公开(公告)日：1991-02-26
申请号：US317877
申请日：1989-03-02
申请人： Peter A. Habitz , Chang-Ming Hsieh , Yi-Shiou Huang
发明人： Peter A. Habitz , Chang-Ming Hsieh , Yi-Shiou Huang
IPC分类号： H01L29/73 , H01L21/331 , H01L21/761 , H01L21/8222 , H01L27/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/6625 , H01L21/761 , H01L29/1008 , Y10S148/01 , Y10S148/096
摘要： A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.

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