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91. 发明授权

US08076732B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08076732B2
公开(公告)日：2011-12-13
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一种属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

92. 发明授权

US07804145B2 Semiconductor device, capacitor, and field effect transistor 有权
标题翻译：半导体器件，电容器和场效应晶体管
公开(公告)号：US07804145B2
公开(公告)日：2010-09-28
申请号：US12388810
申请日：2009-02-19
申请人： Tatsuo Shimizu , Masato Koyama
发明人： Tatsuo Shimizu , Masato Koyama
IPC分类号： H01L29/76
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L28/56 , H01L28/75 , H01L29/517 , H01L29/66833 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.
摘要翻译：可以提供一种具有在半导体和金属之间的界面处优化的连接金属的有效功函数的半导体器件。半导体器件包括：半导体膜; 形成在半导体膜上的氧化物膜，包括Hf和Zr中的至少一种的氧化物膜和选自V，Cr，Mn，Nb，Mo，Tc，W和Re中的至少一种元素被添加到氧化膜; 和形成在氧化物膜上的金属膜。

93. 发明申请

US20090321844A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090321844A1
公开(公告)日：2009-12-31
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

94. 发明申请

US20060289863A1 Semiconductor device evaluation apparatus and semiconductor device evaluation method 失效
标题翻译：半导体装置评估装置及半导体装置的评价方法
公开(公告)号：US20060289863A1
公开(公告)日：2006-12-28
申请号：US11472449
申请日：2006-06-22
申请人： Ryosuke Iijima , Masato Koyama
发明人： Ryosuke Iijima , Masato Koyama
IPC分类号： H01L23/58
CPC分类号： G01R31/2621 , H01L2924/0002 , H01L2924/00
摘要： An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected to a first source/drain region of the field-effect transistor. The switch can be electrically connected to a second source/drain region of the field-effect transistor. The switch switches between a connection state and a disconnection state. The first constant-voltage source can be electrically connected to the second source/drain region through the switch.
摘要翻译：用于评估场效应晶体管的装置包括脉冲发生器，电流/电压转换器，开关和第一恒压源。脉冲发生器可以电连接到场效应晶体管的栅电极。电流/电压转换器包括输入端子。输入端子可以电连接到场效应晶体管的第一源极/漏极区域。开关可以电连接到场效应晶体管的第二源/漏区。交换机在连接状态和断开状态之间切换。第一恒压源可以通过开关电连接到第二源极/漏极区域。

95. 发明申请

US20060186489A1 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US20060186489A1
公开(公告)日：2006-08-24
申请号：US11407077
申请日：2006-04-20
申请人： Masahiro Koike , Masato Koyama , Tsunehiro Ino , Yuuichi Kamimuta , Akira Takashima , Masamichi Suzuki , Akira Nishiyama
发明人： Masahiro Koike , Masato Koyama , Tsunehiro Ino , Yuuichi Kamimuta , Akira Takashima , Masamichi Suzuki , Akira Nishiyama
IPC分类号： H01L29/94
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.

96. 发明授权

US07053455B2 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US07053455B2
公开(公告)日：2006-05-30
申请号：US10772280
申请日：2004-02-06
申请人： Masahiro Koike , Masato Koyama , Tsunehiro Ino , Yuuichi Kamimuta , Akira Takashima , Masamichi Suzuki , Akira Nishiyama
发明人： Masahiro Koike , Masato Koyama , Tsunehiro Ino , Yuuichi Kamimuta , Akira Takashima , Masamichi Suzuki , Akira Nishiyama
IPC分类号： H01L29/94 , H01L31/62
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.

97. 发明申请

US20050184346A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050184346A1
公开(公告)日：2005-08-25
申请号：US11052036
申请日：2005-02-08
申请人： Masato Koyama , Akira Nishiyama , Yuuichi Kamimuta
发明人： Masato Koyama , Akira Nishiyama , Yuuichi Kamimuta
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/01 , H01L27/092 , H01L29/417 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/823864
摘要： A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate insulating film to sandwich the gate electrode in a gate length direction, second gate side walls which sandwich the gate electrode and the first gate side wall, first diffused layers formed on the surface of the silicon substrate to sandwich the channel region, second diffused layers which sandwich the channel region and the first diffused layer and have a larger depth than that of the first diffused layer, and low resistance layers which are formed between the first diffused layer and the second gate side wall and contain nitride, boride or carbide of Ti, Zr, Hf or Ta.
摘要翻译：半导体器件包括硅衬底，形成在硅衬底的表面中的沟道区，形成在沟道区上的栅极绝缘膜，形成在栅极绝缘膜上的栅极，形成在栅极绝缘膜上的第一栅极侧壁夹着栅极电极和第一栅极侧壁的第二栅极侧壁，形成在硅衬底的表面上以夹持沟道区域的第一扩散层，夹着所述栅极电极和第二栅极侧壁的第二扩散层，沟道区域和第一扩散层，并且具有比第一扩散层的深度更大的深度，以及形成在第一扩散层和第二栅极侧壁之间的低电阻层，并且包含Ti，Zr的氮化物，硼化物或碳化物， Hf或Ta。

98. 发明授权

US6088246A Method of and device for controlling pulse width modulation inverter 失效
标题翻译：控制脉宽调制逆变器的方法和装置
公开(公告)号：US6088246A
公开(公告)日：2000-07-11
申请号：US98643
申请日：1998-06-17
申请人： Miho Okuyama , Masato Koyama
发明人： Miho Okuyama , Masato Koyama
IPC分类号： H02M7/48 , H02M7/5395 , H02P27/08 , H02M1/12
CPC分类号： H02M7/5395 , H02M7/53873 , H02M1/44 , H02M2007/53876
摘要： A method of controlling a pulse width modulation or PWM inverter apparatus that generates and controls AC output voltages with PWM control, comprises the steps of: generating a reference voltage vector for setting the AC output voltages; and changing timing of the generation of the AC output voltages during a predetermined period of time determined by a carrier signal at predetermined intervals determined by the carrier signal without changing the pulse widths of the AC output voltages determined by the PWM control so that a vector representing the averages of instantaneous amplitudes of the AC output voltages for a predetermined period of time agrees with the reference voltage vector, and so that the spectra of high-frequency components of each of the AC output voltages are spread out over a predetermined wide range of frequencies.
摘要翻译：一种通过PWM控制来产生和控制AC输出电压的脉宽调制或PWM逆变器装置的控制方法，包括以下步骤：产生用于设定交流输出电压的参考电压矢量; 以及在由载波信号确定的预定间隔由载波信号确定的预定时段期间改变AC输出电压的产生的定时，而不改变由PWM控制确定的AC输出电压的脉冲宽度，使得代表 AC输出电压在预定时间段内的瞬时幅度的平均值与参考电压矢量一致，并且使得每个AC输出电压的高频分量的频谱在预定的宽频率范围内展开。

99. 发明授权

US5247237A Control device of induction motor 失效
标题翻译：电感电机的控制装置
公开(公告)号：US5247237A
公开(公告)日：1993-09-21
申请号：US928052
申请日：1992-08-11
申请人： Masato Koyama , Akira Imanaka
发明人： Masato Koyama , Akira Imanaka
IPC分类号： H02P27/06 , H02H7/08
CPC分类号： H02H7/0833 , H02P21/08 , H02P21/22 , H02P31/00
摘要： An object of the invention is to provide a control device of an induction motor where an inverter circuit can be protected from overcurrent by stable current limitation operation not only at steady operation but also at rapid acceleration/deceleration or at regenerative braking. A current component calculation circuit calculates a first current component from primary current detected by a current detector and output frequency. A correction frequency calculation circuit calculates a frequency correction value using a current limit value and the first current component according to prescribed function calculation. A subtractor subtracts the frequency correction value from a primary frequency command value. A voltage component calculation circuit calculates a primary voltage component command value according to the subtracted output. A primary voltage command calculation circuit calculates a primary voltage command value of the induction motor from the subtracted output and the primary voltage component command value and outputs it to a voltage conversion circuit.
摘要翻译：本发明的目的是提供一种感应电动机的控制装置，其中不仅在稳定运行时，而且在快速加速/减速或再生制动下，通过稳定的电流限制操作可以防止逆变器电路的过流。电流分量计算电路根据电流检测器检测到的一次电流和输出频率来计算第一电流分量。校正频率计算电路根据规定的功能计算，使用电流限制值和第一电流分量来计算频率校正值。减法器从主频率指令值中减去频率校正值。电压分量计算电路根据相减输出来计算一次电压分量指令值。一次电压指令计算电路从减法输出和一次电压分量指令值计算感应电机的一次电压指令值，并将其输出到电压转换电路。

100. 发明授权

US5189603A DC to AC electric power converting apparatus 失效
标题翻译：直流到交流电力转换装置
公开(公告)号：US5189603A
公开(公告)日：1993-02-23
申请号：US756426
申请日：1991-09-09
申请人： Nobuo Sashida , Kazunori Sanada , Masato Koyama
发明人： Nobuo Sashida , Kazunori Sanada , Masato Koyama
IPC分类号： H02M5/27 , H02M7/48
CPC分类号： H02M7/4807
摘要： A DC-to-AC electric power converting apparatus including an invertor circuit having a plurality of switching elements, a transformer connected to the invertor circuit, and a cyclo-converter circuit for converting the frequency of the output from the transformer. A carrier signal generator is provided for generating a carrier signal of a predetermined frequency. An invertor switching circuit for controlling the switching operation of a plurality of the switching elements of the invertor circuit in synchronization with the carrier signal and switching a plurality of the switching elements of the invertor circuit in a period in which an electric current is not substantially passed through the invertor circuit; a reference voltage signal generating circuit for generating a reference voltage signal for the AC voltage to be transmitted from the cyclo-converter circuit; and a switching signal generating circuit for generating a control signal for controlling the cyclo-converter circuit in response to the reference voltage signal generated by the reference voltage signal generating circuit and the carrier signal generated by the carrier signal generator.

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