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91. 发明授权

US08010813B2 Structure for system for extending the useful life of another system 失效
标题翻译：用于延长系统使用寿命的系统结构
公开(公告)号：US08010813B2
公开(公告)日：2011-08-30
申请号：US12051001
申请日：2008-03-19
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
IPC分类号： G06F1/00 , G06F11/00
CPC分类号： H03K19/00392
摘要： Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.
摘要翻译：公开了一种用于相关联的第一系统的设计结构，用于在存在导致在系统设备内展现性能下降和恢复性能的现象的情况下延长第二系统的产品寿命。第一系统包括并入第二系统中的重复设备（例如，在共享总线上）。这些重复设备适于在该第二系统内独立地执行相同的功能。参考信号发生器，参考信号比较器，功率控制器和状态机组合起来可以适应于基于性能下降的测量来在复制设备之间的第二系统内的相同功能的无缝切换性能，以允许设备恢复。状态机可访问的预定策略指示何时以及是否启动切换。

92. 发明授权

US07949978B2 Structure for system architectures for and methods of scheduling on-chip and across-chip noise events in an integrated circuit 有权
标题翻译：用于系统架构的结构以及在集成电路中调度片上和跨芯片噪声事件的方法
公开(公告)号：US07949978B2
公开(公告)日：2011-05-24
申请号：US11934804
申请日：2007-11-05
申请人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
发明人： Corey K. Barrows , Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly , Paul S. Zuchowski
IPC分类号： G06F17/50 , H03K19/003
CPC分类号： G06F17/505
摘要： A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.
摘要翻译：一种设计结构集成电路（IC）系统架构，其允许通过提供一种方法来减少片上或跨芯片的瞬态噪声预算，以避免来自至少两个功能逻辑块（即噪声贡献者）的同时高电流需求事件，被披露。 IC系统架构的实施例包括至少一个噪声事件仲裁器和至少两个噪声贡献器块。调度片上噪声事件以避免同时有效的瞬态噪声事件的方法可以包括但不限于：噪声事件仲裁器同时从多个噪声贡献者接收多个请求操作的请求; 噪声事件仲裁者确定每个噪声贡献者何时可以基于预先建立的dI / dt预算执行操作; 噪声事件仲裁器通知每个噪声贡献者关于何时授权执行其操作。

93. 发明授权

US07941772B2 Dynamic critical path detector for digital logic circuit paths 有权
标题翻译：用于数字逻辑电路路径的动态关键路径检测器
公开(公告)号：US07941772B2
公开(公告)日：2011-05-10
申请号：US11834110
申请日：2007-08-06
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G01R31/3187 , G06F11/1608 , G06F11/1695 , G06F2217/84
摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.
摘要翻译：用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。该方法包括将第一和第二闩锁放置在关键路径附近。第一锁存器具有包括关键路径上的数据值的输入。该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状况，以及执行预定的校正衡量关键路径。

94. 发明申请

US20090276644A1 STRUCTURE FOR SEMICONDUCTOR POWER DISTRIBUTION AND CONTROL 审中-公开
标题翻译：用于半导体功率分配和控制的结构
公开(公告)号：US20090276644A1
公开(公告)日：2009-11-05
申请号：US12114038
申请日：2008-05-02
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A design structure for dynamic integrated circuit power distribution and control is disclosed. The design structure includes an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits. The design structure also includes a first integrated circuit that includes an IC power control unit coupled to the external power consumption target generator. The first integrated circuit also includes a first plurality of functional units, each functional unit of the first plurality including a unit power level control and a first power control grid coupling the IC power control unit to one or more of the first plurality of functional units. The IC power control unit is configured to generate a mode control signal which places at least one of plurality of functional units into a first mode of operation based upon the power consumption target.
摘要翻译：公开了一种用于动态集成电路配电和控制的设计结构。该设计结构包括被配置为产生一个或多个集成电路的功耗目标的外部功耗目标发生器。该设计结构还包括第一集成电路，其包括耦合到外部功耗目标发生器的IC功率控制单元。第一集成电路还包括第一多个功能单元，第一多个功能单元的每个功能单元包括单元功率电平控制和将IC功率控制单元耦合到第一多个功能单元中的一个或多个的第一功率控制网格。 IC功率控制单元被配置为基于功耗目标产生将多个功能单元中的至少一个功能单元置于第一操作模式的模式控制信号。

95. 发明申请

US20090150726A1 METHOD AND SYSTEM FOR EXTENDING THE USEFUL LIFE OF ANOTHER SYSTEM 有权
标题翻译：用于延长其他系统有用寿命的方法和系统
公开(公告)号：US20090150726A1
公开(公告)日：2009-06-11
申请号：US12138480
申请日：2008-06-13
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
IPC分类号： G06F11/30
CPC分类号： G06F11/008
摘要： Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.
摘要翻译：公开了一种方法和相关联的第一系统的实施例，用于在存在导致在系统设备内展现性能下降和恢复性能的现象的情况下延长第二系统的产品寿命。第一系统包括并入第二系统中的重复设备（例如，在共享总线上）。这些重复设备适于在该第二系统内独立地执行相同的功能。参考信号发生器，参考信号比较器，功率控制器和状态机组合起来可以适应于基于性能下降的测量来在复制设备之间的第二系统内的相同功能的无缝切换性能，以允许设备恢复。状态机可访问的预定策略指示何时以及是否启动切换。

96. 发明申请

US20090058504A1 SELF-POWERED VOLTAGE ISLANDS ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路中的自供电电压岛
公开(公告)号：US20090058504A1
公开(公告)日：2009-03-05
申请号：US11849463
申请日：2007-09-04
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Peter A. Twombly
IPC分类号： G05F1/10
CPC分类号： G06F1/263 , G06F1/266
摘要： The present disclosure is directed to self-powered voltage islands on an integrated circuit. A structure in accordance with an embodiment includes: an integrated circuit including a power source; a voltage island; and an on-board power source provided on the voltage island for powering the voltage island independently of the power source of the integrated circuit.
摘要翻译：本公开涉及集成电路上的自供电电压岛。根据实施例的结构包括：包括电源的集成电路; 电压岛; 以及设置在电压岛上的板载电源，用于独立于集成电路的电源为电压岛供电。

97. 发明授权

US07437620B2 Method and system for extending the useful life of another system 失效
标题翻译：延长其他系统使用寿命的方法和系统
公开(公告)号：US07437620B2
公开(公告)日：2008-10-14
申请号：US11164646
申请日：2005-11-30
申请人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Stephen G. Shuma , Oscar C. Strohacker , Mark S. Styduhar , Peter A. Twombly , Andrew S. Wienick , Paul S. Zuchowski
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.
摘要翻译：公开了一种方法和相关联的第一系统的实施例，用于在存在导致在系统设备内展现性能下降和恢复性能的现象的情况下延长第二系统的产品寿命。第一系统包括并入第二系统中的重复设备（例如，在共享总线上）。这些重复设备适于在该第二系统内独立地执行相同的功能。参考信号发生器，参考信号比较器，功率控制器和状态机组合起来可以适应于基于性能下降的测量来在复制设备之间的第二系统内的相同功能的无缝切换性能，以允许设备恢复。状态机可访问的预定策略指示何时以及是否启动切换。

98. 发明申请

US20080215923A1 DESIGN STRUCTURE FOR TASK BASED DEBUGGER (TRANSACTION-EVENT -JOB-TRIGGER) 失效
标题翻译：基于任务调度器的设计结构（交易活动 - 手动触发）
公开(公告)号：US20080215923A1
公开(公告)日：2008-09-04
申请号：US12050982
申请日：2008-03-19
申请人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Charles S. Woodruff
IPC分类号： G06F11/30
CPC分类号： G06F17/5022 , G06F2217/14
摘要： Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.
摘要翻译：公开了用于基于任务的调试器（事务 - 事件 - 作业触发）的装置的设计结构。更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。核心连接到链接功能调试逻辑元件的互连结构。每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件。

99. 发明授权

US6097241A ASIC low power activity detector to change threshold voltage 有权
标题翻译： ASIC低功率活动检测器来改变阈值电压
公开(公告)号：US6097241A
公开(公告)日：2000-08-01
申请号：US159898
申请日：1998-09-24
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1/32 , H03K3/01
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要翻译：诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。

100. 发明授权

US08452566B2 Warranty monitoring and enforcement for integrated circuit and related design structure 失效
标题翻译：集成电路和相关设计结构的保修监控和执行
公开(公告)号：US08452566B2
公开(公告)日：2013-05-28
申请号：US12113974
申请日：2008-05-02
申请人： Kenneth J. Goodnow , Suzanne Granato , Eze Kamanu , Todd E. Leonard , Ramnath Ravindran , Kyle E. Schneider , Peter A. Twombly
发明人： Kenneth J. Goodnow , Suzanne Granato , Eze Kamanu , Todd E. Leonard , Ramnath Ravindran , Kyle E. Schneider , Peter A. Twombly
IPC分类号： G06F3/00 , G06F3/01 , G06F3/023 , G06F3/03
CPC分类号： G06F17/5045 , G06Q10/06 , G06Q50/18
摘要： An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.
摘要翻译：公开了包括保修和执行系统的集成电路（IC）以及相关设计结构和HDL设计结构。在一个实施例中，IC包括用于获得IC参数值的参数获取器; 保存数据存储系统，用于存储有关IC的保修限制数据; 比较器，用于通过将参数的值与相应的保修限制进行比较来确定是否超过了保修期限; 以及根据超出的保修期限采取规定行动的行动者。

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