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91. 发明授权

US06912157B2 Semiconductor memory device using only single-channel transistor to apply voltage to selected word line 有权
公开(公告)号：US06912157B2
公开(公告)日：2005-06-28
申请号：US10607153
申请日：2003-06-27
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C11/413 , G11C16/04 , G11C16/06 , G11C16/08 , H01L27/115
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/3459 , H01L27/115
摘要： A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

92. 发明申请

US20050063209A1 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US20050063209A1
公开(公告)日：2005-03-24
申请号：US10957722
申请日：2004-10-05
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/00 , G11C5/06
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. By use of the semiconductor memory device, occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array can be prevented, and the manufacturing yield can be made high and the operation reliability can be made high without substantially increasing the chip size.
摘要翻译：提供一种半导体存储器件，其能够防止由于存储单元阵列的端部区域中的蚀刻精度降低而导致的缺陷的发生，并且实现了具有高操作可靠性和高制造成品率的便宜的芯片。第一块由具有连接的多个存储单元的第一存储单元单元构成，第二块由具有连接的多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块在其两端部分，并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。通过使用半导体存储器件，可以防止由存储单元阵列的端部区域中的蚀刻精度降低引起的缺陷的发生，并且可以使制造成品率高，并且可以使操作可靠性高而无需高大大增加芯片尺寸。

93. 发明授权

US06512253B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06512253B2
公开(公告)日：2003-01-28
申请号：US09976317
申请日：2001-10-15
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L2710
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

94. 发明授权

US06418058B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06418058B1
公开(公告)日：2002-07-09
申请号：US09994828
申请日：2001-11-28
申请人： Koji Sakui , Hiroshi Nakamura , Kenichi Imamiya
发明人： Koji Sakui , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C1606
CPC分类号： G11C16/3454
摘要： In NAND type EEPROM capable of high-speed rewriting by ensuring that the memory cell current during write verify read-out operation is larger than that during normal data read-out operation, a NAND cell is composed of a plurality of serially connected memory cells (MC0 through MC31) and selection transistors (SST and GST). During data write operation, a voltage (Vpgm) is applied to a selected word line of a selected block, and a pass voltage (Vpass2) is applied to non-selected word lines to introduce electrons to the floating gate of the selected memory cell. In verify read-out operation after data write operation, a verify read-out voltage is applied to the selected word line and a pass voltage (Vpass3) to non-selected word lines. The pass voltage (Vpass3) applied to non-selected word lines during verify read-operation is higher than the pass voltage (Vpass1) applied to non-selected word lines during normal data read-out operation.

95. 发明授权

US06353242B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06353242B1
公开(公告)日：2002-03-05
申请号：US09274481
申请日：1999-03-23
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有多个接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

96. 发明授权

US08513726B2 EEPROM with increased reading speed 有权
标题翻译： EEPROM读取速度更快
公开(公告)号：US08513726B2
公开(公告)日：2013-08-20
申请号：US13370064
申请日：2012-02-09
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C11/5621 , G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
摘要翻译：在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压Vread与电压Vsg1，Vsg2 在所选择的块中选择晶体管的选择栅极，从而使得可以实现高速读取，而不会导致插入在选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。选择晶体管的栅极。

97. 发明授权

US08350309B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08350309B2
公开(公告)日：2013-01-08
申请号：US13310148
申请日：2011-12-02
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： G11C16/0483 , G11C16/10
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

98. 发明授权

US08331124B2 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US08331124B2
公开(公告)日：2012-12-11
申请号：US13071729
申请日：2011-03-25
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C5/06
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

99. 发明授权

US08084802B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08084802B2
公开(公告)日：2011-12-27
申请号：US13025957
申请日：2011-02-11
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

100. 发明申请

US20110216594A1 SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE 有权
标题翻译：仅使用单通道晶体管将电压施加到选定字线的半导体存储器件
公开(公告)号：US20110216594A1
公开(公告)日：2011-09-08
申请号：US13109694
申请日：2011-05-17
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/3459 , H01L27/115
摘要： A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.
摘要翻译：半导体存储器件具有存储单元阵列，第一导电类型的第一晶体管，第二导电类型的第二晶体管和第一导电类型的第三晶体管。第一晶体管的源极或漏极连接到每条字线。第二晶体管的漏极连接到第一晶体管的栅极。第三晶体管的源极连接到第一晶体管的栅极。第二晶体管和第三晶体管的栅极不连接，第二晶体管的源极不连接到第三晶体管的漏极，并且第二晶体管的栅极和第三晶体管的漏极具有不同的电压电平彼此相反的逻辑水平。

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