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91. 发明授权

US07796429B2 Memory controller controlling semiconductor storage device and semiconductor device 失效
公开(公告)号：US07796429B2
公开(公告)日：2010-09-14
申请号：US12039254
申请日：2008-02-28
申请人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
发明人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

92. 发明申请

US20100146228A1 MEMORY SYSTEM AND CONTROL METHOD THEREOF 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US20100146228A1
公开(公告)日：2010-06-10
申请号：US12705431
申请日：2010-02-12
申请人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
发明人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
IPC分类号： G06F12/00 , G11C16/04 , G06F11/00
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/76
摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.
摘要翻译：一种存储器系统，包括：包括作为数据擦除单元的块的非易失性存储器，测量擦除每个块中的数据的擦除时间的测量单元;具有块表的块控制器，其将指示空闲状态之一的状态值和具有每个块的擦除时间的使用状态，检测在短时间内共同发生重写的块的检测器，选择具有旧擦除时间的空闲块作为第一块的第一选择器，选择如果第一块被包括在由检测器检测到的块中，则将具有旧擦除时间的块用作第二块;以及调平单元，其将第二块中的数据移动到第一块。

93. 发明申请

US20100077266A1 MEMORY SYSTEM AND CONTROL METHOD THEREOF 有权
公开(公告)号：US20100077266A1
公开(公告)日：2010-03-25
申请号：US12551213
申请日：2009-08-31
申请人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
发明人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
IPC分类号： G11C16/04 , G11C16/06 , G11C29/00 , G06F11/00
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/76
摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.

94. 发明授权

US07600140B2 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US07600140B2
公开(公告)日：2009-10-06
申请号：US11778404
申请日：2007-07-16
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.
摘要翻译：通过根据施加在可编程逻辑电路上的处理能力自动改变时钟频率和工作电压，降低功耗的逻辑电路系统。可编程逻辑电路能够动态地实现多个电路功能，并且可以在操作期间改变实现的电路功能。此外，系统具有用于向可编程逻辑电路提供电压的电压供应部分，用于向可编程逻辑电路提供时钟信号的时钟信号提供部分，用于改变可编程逻辑实现的电路功能的改变控制部分电路中的任何一个电路功能，操作时间测量部分，用于分别测量可编程逻辑电路的操作时间以执行分别执行电路功能的处理;以及时钟和电压确定部分，用于确定时钟信号和电压，使用操作时间。

95. 发明授权

US07551478B2 Apparatus, method and computer program product for reading information stored in storage medium 有权
标题翻译：用于读取存储在存储介质中的信息的装置，方法和计算机程序产品
公开(公告)号：US07551478B2
公开(公告)日：2009-06-23
申请号：US11531963
申请日：2006-09-14
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C11/5642 , G11C29/00 , G11C2029/0411 , G11C2211/5634
摘要： An apparatus for reproducing information includes a memory unit which stores charge; a reading unit which obtains an amount of the charge stored in the memory unit, and reads information by determining a value based on a comparison of the amount of the charge with a first threshold; an error detection unit which determines whether the information read has an error; and a threshold generation unit which generates a second threshold having a value different from that of the first threshold used in reading the information, when the error detection unit determines that the information has an error, wherein the reading unit further reads the information by determining a value based on a comparison of the amount of the charge with the second threshold after the error detection unit determines that the information has the error.
摘要翻译：一种用于再现信息的装置包括：存储单元，其存储电荷; 读取单元，其获取存储在存储单元中的电荷量，并且通过基于电荷量与第一阈值的比较来确定值来读取信息; 错误检测单元，其确定读取的信息是否具有错误; 以及阈值生成单元，当所述错误检测单元确定所述信息具有错误时，生成具有与用于读取所述信息的所述第一阈值不同的值的第二阈值，其中所述读取单元还通过确定所述信息来读取所述信息基于在错误检测单元确定信息具有错误之后的电荷量与第二阈值的比较的值。

96. 发明授权

US07434074B2 Logic circuit system and method of changing operating voltage of a programmable logic circuit 失效
公开(公告)号：US07434074B2
公开(公告)日：2008-10-07
申请号：US11778389
申请日：2007-07-16
申请人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku Ohneda , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system with power consumption that is reduced by automatically varying the clock frequency and operating voltage according to processing capability imposed on programmable logic circuits. The programmable logic circuits are capable of achieving plural circuit functions dynamically and can change realized circuit functions during operation. In addition, the system has a voltage supply portion for supplying a voltage to the programmable logic circuits, a clock signal supply portion for supplying a clock signal to the programmable logic circuits, a change control portion for changing the circuit functions realized by the programmable logic circuits to any one of the circuit functions, an operation time measuring portion for measuring the operation times of the programmable logic circuits to perform processing to achieve the circuit functions, respectively, and a clock-and-voltage determination portion for determining the frequency of the clock signal and the voltage, using the operation times.

97. 发明申请

US20070268040A1 LOGIC CIRCUIT SYSTEM AND METHOD OF CHANGING OPERATING VOLTAGE OF A PROGRAMMABLE LOGIC CIRCUIT 失效
标题翻译：逻辑电路系统和可编程逻辑电路的工作电压变化方法
公开(公告)号：US20070268040A1
公开(公告)日：2007-11-22
申请号：US11831722
申请日：2007-07-31
申请人： Taku OHNEDA , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
发明人： Taku OHNEDA , Shinichi Kanno , Masaya Tarui , Yukimasa Miyamoto
IPC分类号： H03K19/173
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3296 , H03K19/0008 , H03K19/0016 , H03K19/1736 , H03K19/17752 , H03K19/17756 , H03K19/17784 , H03K19/17788 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A logic circuit system, having a programmable logic circuit including a circuit configuration including a first set of plural unit circuits and that is reconfigurable during operation, a circuit configuration information supplier configured to supply circuit configuration information about a second set of plural unit circuits to said programmable logic circuit, a change controller configured to change the circuit configuration of said programmable logic circuit from said first set of said plural unit circuits to said second set of said plural unit circuits based on said circuit configuration information, an operation time measurer configured to measure operation times of said first and second set of plural unit circuits, and a clock-and-voltage supplier configured to use said measured operation times to change from a first frequency and voltage value corresponding to said first set to a second frequency and voltage value corresponding to said second set, and to supply a clock signal having said second frequency and voltage value to said programmable logic circuit, thereby varying a programmable logic circuit frequency and voltage value in accordance with variations in said operation times.
摘要翻译：一种逻辑电路系统，具有可编程逻辑电路，该可编程逻辑电路包括电路配置，该电路配置包括第一组多个单元电路，并且可在运行期间重新配置;电路配置信息提供器，被配置为将电路配置信息提供给所述多个单元电路的第二组可编程逻辑电路，变更控制器，被配置为基于所述电路配置信息将所述可编程逻辑电路的电路配置从所述多个单元电路的所述第一组改变为所述多个单元电路的所述第二组;操作时间测量器，所述第一和第二组多个单位电路的操作时间和被配置为使用所述测量的操作时间从对应于所述第一组的第一频率和电压值变化到对应于第二频率和电压值的时钟和电压供应器到第二组，并提供一个时钟信号将所述第二频率和电压值表示为所述可编程逻辑电路，从而根据所述操作时间的变化来改变可编程逻辑电路的频率和电压值。

98. 发明申请

US20070255976A1 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
公开(公告)号：US20070255976A1
公开(公告)日：2007-11-01
申请号：US11819449
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.

99. 发明申请

US20070255975A1 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US20070255975A1
公开(公告)日：2007-11-01
申请号：US11819417
申请日：2007-06-27
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F1/08
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。

100. 发明授权

US07281152B2 Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
标题翻译：处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法
公开(公告)号：US07281152B2
公开(公告)日：2007-10-09
申请号：US10808571
申请日：2004-03-25
申请人： Masaya Tarui , Shinichi Kanno
发明人： Masaya Tarui , Shinichi Kanno
IPC分类号： G06F5/06 , G06F1/00 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor includes a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, the clock signals being supplied newly to the operational processing part.
摘要翻译：处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量来确定时钟信号的新时钟频率，所述时钟信号被新提供给所述操作处理部分。

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