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    • 91. 发明申请
    • Synchronous interface and method of operation
    • 同步接口和操作方法
    • US20060095655A1
    • 2006-05-04
    • US10981043
    • 2004-11-04
    • George MooreTimothy ChristensenBrian Okken
    • George MooreTimothy ChristensenBrian Okken
    • G06F12/14
    • G06F5/10G06F2205/065
    • In one embodiment, an interface facilitates communication of data between a source block and a sink block. The interface comprises a first register element that receives data from the source block via an input line, wherein the first register element changes value when a clock enable signal is applied to the first register element and maintains its value when the clock enable signal is not applied; a first multiplexer coupled to the input line and an output of the first register element; and a first shift register for receiving a signal from the sink block indicating that the sink block is retrieving data from the interface; wherein the first shift register outputs a delayed version of the signal from the sink block to provide the clock enable signal to the first register element and to control an output of the first multiplexer.
    • 在一个实施例中,接口便于在源块和宿块之间的数据通信。 接口包括经由输入线从源块接收数据的第一寄存器元件,其中当时钟使能信号被施加到第一寄存器元件时,第一寄存器元件改变值,并且当不施加时钟使能信号时保持其值 ; 耦合到输入线的第一多路复用器和第一寄存器元件的输出; 以及第一移位寄存器,用于从所述宿块接收指示所述宿块正在从所述接口检索数据的信号; 其中所述第一移位寄存器从所述宿块输出所述信号的延迟版本,以将所述时钟使能信号提供给所述第一寄存器元件并且控制所述第一多路复用器的输出。
    • 95. 发明申请
    • Pipelined accumulators
    • 流水线蓄能器
    • US20050132164A1
    • 2005-06-16
    • US10677995
    • 2003-10-01
    • George MooreJohn SnodderleyHoward Hilton
    • George MooreJohn SnodderleyHoward Hilton
    • G06F7/509G06F15/00G06F15/76
    • G06F7/5095G06F2207/3884
    • Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propagation through the accumulator. While input and output delay registers are used in the accumulator partitions, the output delay registers are not needed if the results of those partitions are not needed in subsequent stages of computation. If phase coherence is not needed, input delay registers may not be needed on accumulator partitions. In the limiting case of one bit per partition, the effective speed of the pipelined accumulator is equivalent to the speed of a single bit accumulator stage.
    • 流水线数字蓄能器。 通过流水线改进用于数字信号处理的并行数字累加器。 累加器被划分成多个流水线级,并且使用流水线延迟来减少通过累加器的进位传播的影响。 虽然在累加器分区中使用输入和输出延迟寄存器,但是如果在后续的计算阶段不需要这些分区的结果,则不需要输出延迟寄存器。 如果不需要相位相干,则在累加器分区上可能不需要输入延迟寄存器。 在每个分区一位的限制情况下,流水线累加器的有效速度等于单位累加器级的速度。
    • 98. 发明授权
    • Method and system for compensating for geometric distortion of images
    • 补偿图像几何失真的方法和系统
    • US5940537A
    • 1999-08-17
    • US586058
    • 1996-01-16
    • Joel H. RegenGeorge Moore
    • Joel H. RegenGeorge Moore
    • G06K9/42G06K9/76
    • G06K9/42
    • A method of and system for compensating for geometric distortion in a two-dimensional image finds fiducial marks in the image plane corresponding to fiducial marks in the object plane. The invention includes performing a matched filter search to locate corner fiducials from an object plane in the image plane. Locating the corner fiducials permits locating the remaining fiducials in the image plane. A centroid calculation makes the location of the fiducials in the image plane more precise and permits the generation of a solution matrix. The solution matrix and a trajectory engine map the pixels in the image plane to compensate for magnification, tilt, pin cushion, barrel, and other types of geometric distortions.
    • 用于补偿二维图像中的几何失真的方法和系统在与对象平面中的基准标记相对应的图像平面中找到基准标记。 本发明包括执行匹配滤波器搜索以从图像平面中的物体平面定位角基准。 找到角基准点可以将剩余的基准点定位在图像平面中。 质心计算使得基准点在图像平面中的位置更精确,并允许生成解矩阵。 解决方案矩阵和轨迹引擎映射图像平面中的像素以补偿放大倍数,倾斜度,针坐垫,筒体和其他类型的几何失真。