专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07212000B2 Detection of a defective disk of a hard disk drive 失效
标题翻译：检测硬盘驱动器的故障磁盘
公开(公告)号：US07212000B2
公开(公告)日：2007-05-01
申请号：US10698866
申请日：2003-10-30
申请人： Geng Wang , Sang Lee
发明人： Geng Wang , Sang Lee
IPC分类号： G01B7/00
CPC分类号： G11B27/36 , G11B20/1816 , G11B2220/2516
摘要： A method and apparatus for detecting a defective disk for a hard disk drive. The method includes placing a disk into a tester so that a first side of the disk is adjacent to a first head of the tester and a second side of the disk is adjacent to a second head. First data is read from the first side of the disk, and second data is read from the second side of the disk. The disk is then flipped so that the second side is adjacent to the first head and the first side is adjacent to the second head. Third data is read from the first side. Fourth data is read from the second side. A first area between a curve generated from the first data and a curve generated from the third data is calculated. Likewise, a second area is calculated between a curve generated from the second data and a curve generated from the fourth data. An average of the first and second areas is then calculated and used to detect a defective disk.
摘要翻译：一种用于检测用于硬盘驱动器的有缺陷的盘的方法和装置。该方法包括将盘放入测试器中，使得盘的第一侧与测试器的第一头相邻，并且盘的第二侧与第二头相邻。从盘的第一侧读取第一数据，从盘的第二侧读取第二数据。然后将盘翻转，使得第二侧与第一头相邻，并且第一侧与第二头相邻。从第一侧读取第三数据。从第二侧读取第四数据。计算从第一数据生成的曲线与从第三数据生成的曲线之间的第一区域。类似地，在从第二数据产生的曲线和从第四数据生成的曲线之间计算第二区域。然后计算第一和第二区域的平均值，并用于检测有缺陷的盘。

92. 发明申请

US20070051996A1 METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS 有权
标题翻译：形成具有双功能功能材料的MOSFET的方法
公开(公告)号：US20070051996A1
公开(公告)日：2007-03-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

93. 发明申请

US20060258060A1 Gate controlled floating well vertical MOSFET 审中-公开
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US20060258060A1
公开(公告)日：2006-11-16
申请号：US11487809
申请日：2006-07-17
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L21/339
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管在通常施加到存储和控制单元的两个门的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

94. 发明授权

US07089649B2 Method of estimating a thermal pole tip protrusion for a head gimbal assembly 失效
标题翻译：估计头部万向节组件的热极尖突起的方法
公开(公告)号：US07089649B2
公开(公告)日：2006-08-15
申请号：US10256553
申请日：2002-09-26
申请人： Geng Wang , Hae Jung Lee , Keung Youn Cho , Sang Lee
发明人： Geng Wang , Hae Jung Lee , Keung Youn Cho , Sang Lee
IPC分类号： G11B5/127 , H04R31/00
CPC分类号： G11B5/3136 , G11B5/012 , G11B5/455 , G11B5/4806 , G11B5/4833 , G11B5/484 , Y10T29/49025 , Y10T29/49027 , Y10T29/49028 , Y10T29/49032 , Y10T29/49036
摘要： Thermal pole tip protrusion is caused by materials in and around head slider expanding during write operations till they protrude, leading to contact with the rotating disk surface, altering the flying height and often wearing down part of the disk surface. While well known that read-write heads expand during writing, the inventors who recognized this situation's significance, particularly as flying height decreases and data rates increase, both required for high areal density disk drives. The inventors realized that they could detect the problem at the spin stand level by testing head gimbal assemblies to reliably, and inexpensively, predict the tendency for thermal pole tip protrusion. This leads to selection of head gimbal assemblies, which do not have the thermal pole tip protrusion tendency. The selected head gimbal assemblies have better reliability, as do actuators and disk drives made with the selected head gimbal assemblies.
摘要翻译：热敏头尖突起由写入操作期间头部滑块内和周围的材料引起，直到它们突出，导致与旋转盘表面接触，改变飞行高度并经常磨损盘表面的一部分。虽然众所周知，读写头在写入期间扩展，但是认识到这种情况的重要性的发明人，特别是当高密度磁盘驱动器都需要飞行高度降低和数据速率增加时。本发明人意识到，它们可以通过测试头万向架组件可靠且廉价地预测热极尖端突起的趋势来检测旋转台水平的问题。这导致了不具有热极尖突起倾向的头万向节组件的选择。所选择的头万向架组件具有更好的可靠性，与使用所选择的头万向架组件制造的致动器和磁盘驱动器一样。

95. 发明申请

US20060102945A1 STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT 有权
标题翻译：精密深度电阻测量的结构和方法
公开(公告)号：US20060102945A1
公开(公告)日：2006-05-18
申请号：US10904528
申请日：2004-11-15
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L29/94
CPC分类号： H01L22/34 , H01L27/1087 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.
摘要翻译：用于实现在半导体器件中形成的深沟槽的电阻测量的测试结构包括形成在半导体衬底内的一对深沟槽。一对深沟槽具有在其侧表面和底表面上形成的电介质材料，并且在其中包括导电填充材料。一对深沟槽的底部部分彼此合并，以提供穿过其中的导电路径。

96. 发明申请

US20060024877A1 High performance embedded dram technology with strained silicon 失效
标题翻译：具有应变硅的高性能嵌入式显示技术
公开(公告)号：US20060024877A1
公开(公告)日：2006-02-02
申请号：US10541660
申请日：2003-01-08
申请人： Jack Mandelman , Jeffrey Gambino , Geng Wang
发明人： Jack Mandelman , Jeffrey Gambino , Geng Wang
IPC分类号： H01L21/8238
CPC分类号： H01L27/10894 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3081 , H01L27/10864
摘要： Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.
摘要翻译：半导体器件制造在同一衬底的应变层区域和无应变层的层中。第一半导体器件，例如存储器单元，例如在衬底的无应变层的区域中形成深沟槽存储单元。在相同的衬底中选择性地形成应变层区域。第二半导体器件（66,68,70），例如FET，例如，一个MOSFET逻辑器件，形成在应变层区域中。

97. 发明授权

US09898177B2 Display processing method and portable mobile terminal 有权
公开(公告)号：US09898177B2
公开(公告)日：2018-02-20
申请号：US13824832
申请日：2011-09-21
申请人： Geng Wang , Ran Sun
发明人： Geng Wang , Ran Sun
IPC分类号： G06F3/00 , G06F3/0484 , G06F3/0482 , G06F3/0488
CPC分类号： G06F3/04845 , G06F3/0482 , G06F3/04842 , G06F3/04883 , G06F2203/04104
摘要： A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.

98. 发明申请

US20160188178A1 Display Processing Method And Portable Mobile Terminal 有权
标题翻译：显示处理方法和便携式移动终端
公开(公告)号：US20160188178A1
公开(公告)日：2016-06-30
申请号：US13824832
申请日：2011-09-21
申请人： Geng Wang , Ran Sun
发明人： Geng Wang , Ran Sun
IPC分类号： G06F3/0484 , G06T7/00 , G06F3/0482 , G06F3/0488
CPC分类号： G06F3/04845 , G06F3/0482 , G06F3/04842 , G06F3/04883 , G06F2203/04104
摘要： A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.
摘要翻译：一种应用于便携式移动终端中的显示处理方法，用于在便携式移动终端的触摸屏上显示多个对象。该方法包括获得触摸点，该触摸点是当操作对象接触/几乎触摸触摸屏时创建的点; 以触摸点为中心确定预设区域; 确定在多个对象中的第一对象和第二对象，每个对象至少在一个点上与预设区域相交; 确定所述第一对象的移动的第一信息，所述第一信息指示将所述第一对象从第一位置移动到第二位置，所述第一位置是在所述触摸屏上显示的所述第一对象的原始位置; 以及根据第一信息将第一物体从第一位置移动到第二位置。

99. 发明授权

US08536649B2 Method to reduce threshold voltage variability with through gate well implant 失效
标题翻译：通过栅极井注入降低阈值电压变化的方法
公开(公告)号：US08536649B2
公开(公告)日：2013-09-17
申请号：US13608860
申请日：2012-09-10
申请人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
发明人： Geng Wang , Joseph Ervin , Jeffrey B. Johnson , Paul C. Parries
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , H01L21/2652 , H01L29/78696
摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.
摘要翻译：本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。存在于半导体层的沟道部分上的栅极结构。第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

100. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式