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91. 发明授权

US08680573B2 Diode-triggered silicon controlled rectifier with an integrated diode 有权
标题翻译：具二极管的二极管触发式可控硅整流器
公开(公告)号：US08680573B2
公开(公告)日：2014-03-25
申请号：US13455653
申请日：2012-04-25
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L29/66
CPC分类号： H01L21/8222 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.
摘要翻译：可控硅整流器的器件结构，设计结构和制造方法。第一导电类型的阱形成在器件区域中，其可以由绝缘体上半导体衬底的器件层限定。在井中形成第二导电类型的掺杂区域。在器件区域中形成可控硅整流器的阴极和二极管的阴极。可控硅整流器包括阱的第一部分和由掺杂区域的第一部分组成的阳极。二极管包括阱的第二部分和由掺杂区域的第二部分组成的阳极。

92. 发明授权

US08614121B2 Method of manufacturing back gate triggered silicon controlled rectifiers 有权
标题翻译：制造背栅触发硅控整流器的方法
公开(公告)号：US08614121B2
公开(公告)日：2013-12-24
申请号：US13306488
申请日：2011-11-29
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/00
CPC分类号： H01L27/0262 , H01L29/7436
摘要： Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions.
摘要翻译：背栅触发硅控整流器（SCR）及其制造方法。该方法包括在绝缘体上硅（SOI）衬底的半导体层中形成第一扩散型和第二扩散型。该方法还包括在SOI衬底的绝缘体层之下的衬底中形成第一扩散型的背栅。该方法还包括分别形成与第二扩散型和第一扩散型相邻的第一掺杂剂类型和第二掺杂剂类型的凸起扩散区域。后栅极形成为覆盖第二扩散型，第一扩散型和第二掺杂型的凸起扩散区。

93. 发明授权

US08598660B2 Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage 有权
公开(公告)号：US08598660B2
公开(公告)日：2013-12-03
申请号：US13150612
申请日：2011-06-01
申请人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
发明人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835 , H01L29/7843
摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

94. 发明授权

US08597993B2 Electrostatic discharge (ESD) device and method of fabricating 有权
标题翻译：静电放电（ESD）器件及其制造方法
公开(公告)号：US08597993B2
公开(公告)日：2013-12-03
申请号：US12048461
申请日：2008-03-14
申请人： Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
发明人： Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
IPC分类号： H01L21/8238
CPC分类号： H01L27/0259 , H01L27/0277 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
摘要翻译：通过将三极管内的pFET与NMOSFET或n-p-n之间的PMOS双极集成在一起来制造集成电路芯片中的静电放电（EDS）电路的结构和方法。横向双极性优选地包括在电路的I / O和/或VDD处的二极管。

95. 发明授权

US08513738B2 ESD field-effect transistor and integrated diffusion resistor 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US08513738B2
公开(公告)日：2013-08-20
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/60
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

96. 发明授权

US08390068B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US08390068B2
公开(公告)日：2013-03-05
申请号：US13361051
申请日：2012-01-30
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L27/01 , H01L29/74 , H01L23/62
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

97. 发明授权

US08299533B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08299533B2
公开(公告)日：2012-10-30
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/62
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

98. 发明授权

US08216909B2 Field effect transistor with air gap dielectric 有权
标题翻译：具有气隙电介质的场效应晶体管
公开(公告)号：US08216909B2
公开(公告)日：2012-07-10
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti , Yun Shi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

99. 发明授权

US08169760B2 Signal and power supply integrated ESD protection device 有权
标题翻译：信号和电源集成ESD保护装置
公开(公告)号：US08169760B2
公开(公告)日：2012-05-01
申请号：US12355889
申请日：2009-01-19
申请人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
发明人： Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
IPC分类号： H02H9/00 , H02H3/22 , H02H3/20
CPC分类号： H01L27/0266
摘要： An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.
摘要翻译：集成电路，形成集成电路的设计结构和方法，其包括耦合到I / O信号焊盘的信号焊盘ESD和耦合到源VDD的电源ESD。信号垫ESD和电源ESD集成在单个ESD结构中。

100. 发明授权

US08039868B2 Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure 有权
标题翻译：静电放电（ESD）可控硅整流（SCR）结构的结构和方法
公开(公告)号：US08039868B2
公开(公告)日：2011-10-18
申请号：US12342228
申请日：2008-12-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Aniket Srivastava
IPC分类号： H01L29/72 , H01L29/74
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

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