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91. 发明申请

US20050101096A1 SELF-ALIGNED LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：自对准侧向异相双极晶体管
公开(公告)号：US20050101096A1
公开(公告)日：2005-05-12
申请号：US10703284
申请日：2003-11-06
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-Fu Chu
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

92. 发明申请

US20050063944A1 Method of inducing maturation of dendritic cells and uses therefor 审中-公开
标题翻译：诱导树突状细胞成熟的方法及其用途
公开(公告)号：US20050063944A1
公开(公告)日：2005-03-24
申请号：US10666490
申请日：2003-09-19
申请人： Jian Li , Lamine Mbow , Theresa Goletz , David Peritt
发明人： Jian Li , Lamine Mbow , Theresa Goletz , David Peritt
IPC分类号： A61K38/20 , C12N5/0784 , A61K38/19
CPC分类号： A61K38/20 , A61K35/15 , A61K38/19 , A61K2039/5154 , C12N5/0639 , C12N2501/22 , C12N2501/23 , C12N2501/25 , A61K2300/00
摘要： The invention relates to the induction of responses relating to the maturation of dendritic cells, using IL-18 and IL-18 muteins, and compounds, compositions, methods of making and using thereof, including therapeutic methods and products.
摘要翻译：本发明涉及使用IL-18和IL-18突变蛋白对树突状细胞成熟的反应的诱导，以及其制备和使用方法，包括治疗方法和产品的化合物，组合物，方法。

93. 发明授权

US06806771B1 Multimode output stage converting differential to single-ended signals using current-mode input signals 有权
标题翻译：多模输出级使用电流模式输入信号将差分转换为单端信号
公开(公告)号：US06806771B1
公开(公告)日：2004-10-19
申请号：US10159681
申请日：2002-05-31
申请人： Paul Hildebrant , Jian Li , Hans W. Klein
发明人： Paul Hildebrant , Jian Li , Hans W. Klein
IPC分类号： H03G310
CPC分类号： H03F3/45475 , H03F1/3211 , H03F3/3022 , H03F3/45183 , H03F3/45748 , H03F3/45973 , H03F2200/261 , H03F2200/78 , H03F2203/45458 , H03F2203/45526 , H03G3/001
摘要： An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches. The CLDAC uses a digital-to-analog converter (DAC) to perform offset calibration at the differential input of the output amplifier. In addition, the output block is configured to be operational in a number of user-selectable modes, including, in one embodiment, one or more of: a linear (NORM) mode, a comparator (COMP) mode, and an integrator (INT) mode. An amplifier in the output block is variously reconfigured to achieve the selected mode of operation. Also, the output block accommodates an autocalibration (CAL) technique by clamping the single-ended output stage and balancing, through operation of the CLDAC, signals at an input node and at an interstage node of the amplifier.
摘要翻译：用于在系统可编程模拟集成电路的输出块。输出模块具有输出放大器，可接受差分电流模式输入信号，并提供单端输出电压。输出放大器也可选择可操作为线性放大器，积分器或比较器。输出块还包括共模反馈电路（CMFB），模拟微调电路（OATRM），钳位电路和偏移校准电路（CLDAC），全部耦合到输出放大器的差分输入。 CMFB具有与输出放大器的带宽相当的带宽，以及使差分输入能够实现单端输出转换的驱动能力。 CLAMP在比较器模式下连接到差分输入，以避免从过驱动条件恢复缓慢。 OATRM将差分电流强制为差分输入，补偿由各种不匹配产生的（增益无关）偏移电压。 CLDAC使用数模转换器（DAC）在输出放大器的差分输入端执行偏移校准。此外，输出块被配置为可在多个用户可选模式下操作，包括在一个实施例中，一个或多个：线性（NORM）模式，比较器（COMP）模式和积分器（INT ）模式。输出块中的放大器被不同地重新配置以实现所选择的操作模式。此外，输出块通过钳位单端输出级并通过CLDAC的操作在放大器的输入节点和级间节点处的信号进行平衡来适应自动校准（CAL）技术。

94. 发明授权

US06798003B2 Reliable adhesion layer interface structure for polymer memory electrode and method of making same 失效
标题翻译：聚合物记忆电极的可靠粘附层界面结构及其制备方法
公开(公告)号：US06798003B2
公开(公告)日：2004-09-28
申请号：US09909375
申请日：2001-07-20
申请人： Jian Li , Xiao-Chun Mu
发明人： Jian Li , Xiao-Chun Mu
IPC分类号： H01L4700
CPC分类号： H01L27/11507 , H01L27/11502 , Y10S438/939
摘要： A polymer memory device includes two organic adhesion layers that facilitate an integral package comprising a lower and an upper electrode and the ferroelectric polymer memory structure. The ferroelectric polymer memory structure includes crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure includes spin-on and/or Langmuir-Blodgett deposited compositions. A memory system allows the polymer memory device to interface with various existing hosts.
摘要翻译：聚合物存储器件包括两个有机粘合层，其有助于包含下电极和上电极以及铁电聚合物存储器结构的整体封装。铁电聚合物记忆结构包括结晶铁电聚合物层，例如单一和共聚物组合物。该结构包括旋转和/或Langmuir-Blodgett沉积的组合物。存储器系统允许聚合物存储器件与各种现有主机接口。

95. 发明授权

US06734534B1 Microelectronic substrate with integrated devices 有权
标题翻译：具有集成器件的微电子基板
公开(公告)号：US06734534B1
公开(公告)日：2004-05-11
申请号：US09692908
申请日：2000-10-19
申请人： Quat T. Vu , Jian Li , Steven Towle
发明人： Quat T. Vu , Jian Li , Steven Towle
IPC分类号： H05K334
CPC分类号： H01L21/568 , H01L21/56 , H01L21/561 , H01L23/3114 , H01L23/5389 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/19 , H01L2224/20 , H01L2224/211 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/185 , H05K3/4602 , H01L2224/82 , H01L2924/00012
摘要： A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.
摘要翻译：微电子衬底包括设置在微电子衬底芯中的开口内的至少一个微电子管芯，其中封装材料设置在不被微电子管芯占据的开口的部分内，或者多个微电子管芯封装而不具有微电子衬底芯。然后在微电子管芯，封装材料和微电子衬底芯（如果存在）上制造介电材料和导电迹线的互连层以形成微电子衬底。

96. 发明授权

US06645657B2 Sol-gel coated cathode side hardware for carbonate fuel cells 有权
标题翻译：用于碳酸盐燃料电池的溶胶 - 凝胶涂覆阴极侧硬件
公开(公告)号：US06645657B2
公开(公告)日：2003-11-11
申请号：US09848023
申请日：2001-05-03
申请人： Chao Huang , Jian Li
发明人： Chao Huang , Jian Li
IPC分类号： H01M802
CPC分类号： H01M8/0228 , H01M8/0215 , H01M8/0254 , H01M8/142 , H01M2008/147 , Y02E60/526 , Y02P70/56
摘要： A carbonate fuel cell comprising cathode side hardware having a thin coating of a conductive ceramic for providing corrosion resistance and a method of making the same.
摘要翻译：一种碳酸酯燃料电池，其包括具有用于提供耐腐蚀性的导电陶瓷的薄涂层的阴极侧硬件及其制造方法。

97. 发明授权

US06624457B2 Stepped structure for a multi-rank, stacked polymer memory device and method of making same 失效
标题翻译：多级堆叠聚合物存储器件的阶梯结构及其制造方法
公开(公告)号：US06624457B2
公开(公告)日：2003-09-23
申请号：US09909670
申请日：2001-07-20
申请人： Jian Li , Xiao-Chun Mu
发明人： Jian Li , Xiao-Chun Mu
IPC分类号： H01L31119
CPC分类号： G11C11/22 , B82Y10/00 , H01L27/285
摘要： The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.
摘要翻译：铁电聚合物储存装置技术领域本发明涉及一种铁电聚合物储存装置，其包括至少两个层叠的铁电聚合物存储结构，它们被排列在至少两个相应堆叠的拓扑结构之上，该拓扑结构是包括层间电介质层和通孔结构的预制硅衬底腔。

98. 发明授权

US06586822B1 Integrated core microelectronic package 有权
标题翻译：集成核心微电子封装
公开(公告)号：US06586822B1
公开(公告)日：2003-07-01
申请号：US09658819
申请日：2000-09-08
申请人： Quat T. Vu , Jian Li , Qing Ma , Maria V. Henao , Xiao-Chun Mu
发明人： Quat T. Vu , Jian Li , Qing Ma , Maria V. Henao , Xiao-Chun Mu
IPC分类号： H01L2302
CPC分类号： H01L24/19 , H01L21/568 , H01L23/532 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/92 , H01L2224/97 , H01L2924/01005 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19041 , Y10T29/4935 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.
摘要翻译：一种微电子封装，包括设置在微电子封装芯中的开口内的微电子管芯，其中封装材料设置在不被微电子管芯占据的开口部分内。然后在微电子管芯，密封剂材料和微电子封装芯上制造介电材料和导电迹线的堆积层以形成微电子封装。

99. 发明授权

US6153052A Pulping process 有权
标题翻译：制浆工艺
公开(公告)号：US6153052A
公开(公告)日：2000-11-28
申请号：US397074
申请日：1999-09-16
申请人： Corinne Elizabeth Luthe , Richard McKinnon Berry , Jian Li
发明人： Corinne Elizabeth Luthe , Richard McKinnon Berry , Jian Li
IPC分类号： D21C20060101 , D21C1/10 , D21C3/02 , D21C3/22
CPC分类号： D21C1/10 , D21C3/022 , D21C3/224
摘要： An improved pulping process by which pulp yield is increased requires using polysulfide in the cooking liquor and lignocellulosic particles having a maximum thickness of 2 mm.
摘要翻译：提高纸浆产量的改进的制浆过程需要在蒸煮液中使用多硫化物，并且最大厚度为2mm的木质纤维素颗粒。

100. 发明授权

US5310602A Self-aligned process for capping copper lines 失效
标题翻译：自动对线加工铜线
公开(公告)号：US5310602A
公开(公告)日：1994-05-10
申请号：US960627
申请日：1992-10-13
申请人： Jian Li , James W. Mayer , Evan G. Colgan , Jeffrey P. Gambino
发明人： Jian Li , James W. Mayer , Evan G. Colgan , Jeffrey P. Gambino
IPC分类号： H01L21/768 , H01L23/532 , B32B9/00
CPC分类号： H01L21/76858 , H01L21/76838 , H01L21/76852 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10T428/238 , Y10T428/239 , Y10T428/24917
摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.
摘要翻译：本发明的特征在于制造铜基多层互连的工艺和所得到的制品。由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。铜线约为1微米厚。线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内约五分钟。因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。作为扩散阻挡层，TiN（O）层比TiN更有效。

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