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91. 发明授权

US6081308A Method for manufacturing liquid crystal display 失效
标题翻译：制造液晶显示器的方法
公开(公告)号：US6081308A
公开(公告)日：2000-06-27
申请号：US31445
申请日：1998-02-26
申请人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jueng-Gil Lee
发明人： Chang-Oh Jeong , Yang-Sun Kim , Myung-Koo Hur , Young-Jae Tak , Mun-Pyo Hong , Chi-Woo Kim , Jueng-Gil Lee
IPC分类号： G02F1/1362 , G02F1/1368 , H01L21/28 , H01L23/482 , H01L29/423 , H01L29/49 , G02F1/136 , G02F1/1343 , H01L23/48 , H01L29/04
CPC分类号： G02F1/1368 , G02F1/136286 , H01L21/28008 , H01L23/4827 , H01L29/42384 , H01L29/4908 , G02F1/136227 , G02F2001/13629 , H01L2924/0002
摘要： Since Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single Mo or MoW layer can be used as a wiring by itself of large scale and high resolution liquid crystal. The Mo or MoW layer has the low resistivity of less than 15 .mu..OMEGA.cm and is etched to have a smooth taper angle using an Al etchant with Al or Al alloy. Therefore, it is possible to reduce the number of photolithography processes and to prevent a battery effect and generation of a hillock.
摘要翻译：由于通过调整沉积压力可以沉积Mo或MoW层以便对衬底施加低应力，所以可以使用单个Mo或MoW层作为大规模和高分辨率液晶本身的布线。 Mo或MoW层具有小于15微米欧米伽厘米的低电阻率，并且使用Al或Al合金的Al蚀刻剂被蚀刻以具有平滑的锥角。因此，可以减少光刻工艺的数量并防止电池效应和产生小丘。

92. 发明授权

US09196746B2 Thin film transistor comprising main active layer and sub active layer, and method of manufacturing the same 有权
标题翻译：包括主活性层和次活性层的薄膜晶体管及其制造方法
公开(公告)号：US09196746B2
公开(公告)日：2015-11-24
申请号：US13487409
申请日：2012-06-04
申请人： Hong-Long Ning , Byeong-Beom Kim , Chang-Oh Jeong , Sang-Won Shin , Hyeong-Suk Yoo , Xin-Xing Li , Joon-Yong Park , Hyun-Ju Kang , Su-Kyoung Yang , Kyung-Seop Kim
发明人： Hong-Long Ning , Byeong-Beom Kim , Chang-Oh Jeong , Sang-Won Shin , Hyeong-Suk Yoo , Xin-Xing Li , Joon-Yong Park , Hyun-Ju Kang , Su-Kyoung Yang , Kyung-Seop Kim
IPC分类号： H01L29/10 , H01L29/786
CPC分类号： H01L29/78693 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.
摘要翻译：薄膜晶体管包括在基板上的栅电极，与栅电极电连接并包括暴露的沟道部分的主有源层，与主有源层电连接的源电极，与主有源层电连接的漏电极，源电极并与主有源层电连接，以及与主活性层电连接的子有源层。

93. 发明授权

US08524549B2 Method of fabricating thin-film transistor substrate 有权
标题翻译：制造薄膜晶体管基板的方法
公开(公告)号：US08524549B2
公开(公告)日：2013-09-03
申请号：US13191833
申请日：2011-07-27
申请人： Hyung-Jun Kim , Chang-Oh Jeong , Il-Yong Yoon
发明人： Hyung-Jun Kim , Chang-Oh Jeong , Il-Yong Yoon
IPC分类号： H01L21/268
CPC分类号： H01L21/268 , H01L21/02675 , H01L21/02678 , H01L27/1229 , H01L27/1274 , H01L29/66765 , H01L29/78696
摘要： A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.
摘要翻译：制造薄膜晶体管（TFT）基板的方法包括在基板上形成栅电极; 在栅电极上形成绝缘膜; 在所述绝缘膜上形成非晶半导体图案; 以及形成与所述非晶半导体图案上的漏电极分离的源电极; 在所述非晶半导体图案，所述源电极和所述漏电极上形成包括突起的聚光层; 以及通过向所述聚光层的所述突起照射光而使所述非晶半导体图案的至少一部分结晶。

94. 发明授权

US08492190B2 Method for manufacturing display panel 失效
标题翻译：显示面板制造方法
公开(公告)号：US08492190B2
公开(公告)日：2013-07-23
申请号：US13472716
申请日：2012-05-16
申请人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
发明人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
IPC分类号： H01L29/04
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.
摘要翻译：一种显示面板的制造方法，形成下栅极线，在下栅极线上处理半导体，处理基本上垂直于下栅极线的下数据线，处理具有暴露下栅极线的多个沟槽的绝缘层和较低数据在下数据线上行，直接在下栅极线上和多个沟槽内处理上栅极线，以及直接在下数据线上和多个沟槽内处置上数据线。

95. 发明授权

US07888148B2 Signal line for a display device, etchant, thin film transistor panel, and method for manufacturing the same 有权
标题翻译：用于显示装置，蚀刻剂，薄膜晶体管面板的信号线及其制造方法
公开(公告)号：US07888148B2
公开(公告)日：2011-02-15
申请号：US11850922
申请日：2007-09-06
申请人： Hong-Sick Park , Bong-Kyun Kim , Chang-Oh Jeong , Jong-Hyun Choung , Sun-Young Hong , Won-Suk Shin , Byeong-Jin Lee
发明人： Hong-Sick Park , Bong-Kyun Kim , Chang-Oh Jeong , Jong-Hyun Choung , Sun-Young Hong , Won-Suk Shin , Byeong-Jin Lee
IPC分类号： H01L21/00
CPC分类号： C09K13/08 , G09G2300/0426 , G09G2300/0439 , G09G2320/0223 , H01L23/53238 , H01L27/124 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.
摘要翻译：薄膜面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，包括源电极的数据线和形成的漏电极在所述栅极绝缘层或所述半导体层上形成的像素电极和与所述漏极连接的像素电极，其中所述栅极线和所述数据线和漏极的至少一个包括由钼Mo-Nb铌合金构成的第一导电层，以及由含铜铜金属制成的第二导电层。

96. 发明申请

US20110024759A1 THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR FORMING METAL WIRE THEREOF 审中-公开
标题翻译：薄膜晶体管基板及形成金属线的方法
公开(公告)号：US20110024759A1
公开(公告)日：2011-02-03
申请号：US12901324
申请日：2010-10-08
申请人： Jae-Gab LEE , Chang-Oh Jeong , Myung-Mo Sung , Hee-Jung Yang , Beom-Seok Cho
发明人： Jae-Gab LEE , Chang-Oh Jeong , Myung-Mo Sung , Hee-Jung Yang , Beom-Seok Cho
IPC分类号： H01L29/786 , H01L21/768
CPC分类号： H01L29/78603 , G02F2001/136295 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908 , H01L2224/32245
摘要： The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.
摘要翻译：薄膜晶体管基板及其金属布线方法技术领域本发明涉及薄膜晶体管基板及其金属布线方法，更具体地涉及在基板和金属布线之间包括自组装单层的薄膜晶体管基板及其金属布线。由于本发明的薄膜晶体管基板在Si表面和金属布线之间包含三维交联的自组装单层，因此具有良好的粘附能力和抗扩散能力。

97. 发明授权

US07879662B2 Thin film transistor, thin film transistor substrate including the same and method of manufacturing the same 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管基板及其制造方法
公开(公告)号：US07879662B2
公开(公告)日：2011-02-01
申请号：US12573385
申请日：2009-10-05
申请人： Yang-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
发明人： Yang-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
IPC分类号： H01L21/00
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
摘要翻译：在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案没有蚀刻处理，包括TFT的TFT基板及其制造方法。薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。第三导电层包括铝镍合金，并形成在第二导电层上。

98. 发明授权

US07759738B2 Array substrate and method of manufacturing the same 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US07759738B2
公开(公告)日：2010-07-20
申请号：US12269748
申请日：2008-11-12
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L29/04 , H01L29/10 , H01L29/15
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

99. 发明授权

US07719010B2 Thin film transistor, thin film transistor substrate including the same and method of manufacturing the same 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管基板及其制造方法
公开(公告)号：US07719010B2
公开(公告)日：2010-05-18
申请号：US11932314
申请日：2007-10-31
申请人： Yong-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
发明人： Yong-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
IPC分类号： H01L29/786
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
摘要翻译：在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案没有蚀刻处理，包括TFT的TFT基板及其制造方法。薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。第三导电层包括铝镍合金，并形成在第二导电层上。

100. 再颁专利

USRE40162E1 Thin film transistor array substrate for a liquid crystal display 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列基板
公开(公告)号：USRE40162E1
公开(公告)日：2008-03-25
申请号：US10749153
申请日：2003-12-31
申请人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
发明人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
IPC分类号： H01L29/04 , G02F1/136
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136222 , G02F2001/136231 , G02F2001/13629 , G02F2201/40 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.
摘要翻译：用于液晶显示器的薄膜晶体管衬底包括绝缘衬底和形成在衬底上的栅极线组件。栅极线组件具有双层结构，其具有相对于氧化铟锡具有良好接触特性的较低层，以及表现出低电阻特性的上层。栅极绝缘层，半导体层，接触层以及第一和第二数据线层被栅极线组件依次沉积到衬底上。图案化第一和第二数据线层以形成数据线组件，并且通过数据线组件的图案蚀刻接触层，使得接触层具有与数据线组件相同的图案。钝化层沉积到数据线组件上，并且主要在显示区域和周边区域上通过使用不同光透射掩模在钝化层上形成光致抗蚀剂图案。通过光致抗蚀剂图案蚀刻钝化层和下面的层以形成半导体图案和接触窗口。然后由氧化铟锡或氧化铟锌形成像素电极，辅助栅极焊盘和补充数据焊盘。栅极和数据线组件可以形成为单层结构。在形成像素电极之前，可以在结构化衬底上形成黑色矩阵和滤色器，并且可以在像素电极和数据线之间形成开口部分，以防止可能的短路。

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