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91. 发明申请

US20090008720A1 METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
公开(公告)号：US20090008720A1
公开(公告)日：2009-01-08
申请号：US12211649
申请日：2008-09-16
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/423 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

92. 发明申请

US20090008719A1 METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS 有权
公开(公告)号：US20090008719A1
公开(公告)日：2009-01-08
申请号：US12211647
申请日：2008-09-16
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L27/092 , H01L29/423
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

93. 发明申请

US20080311745A1 High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication 有权
标题翻译：用于pFET的高温加工兼容金属栅电极和制造方法
公开(公告)号：US20080311745A1
公开(公告)日：2008-12-18
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, JR. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/44
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译：描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。这些金属的工作功能使其与当前的pFET要求兼容。例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术当Re沉积时使用材料。

94. 发明申请

US20080272438A1 CMOS Circuits with High-K Gate Dielectric 审中-公开
标题翻译：具有高K栅介质的CMOS电路
公开(公告)号：US20080272438A1
公开(公告)日：2008-11-06
申请号：US11743589
申请日：2007-05-02
申请人： Bruce B. Doris , Charlotte DeWan Adams , Eduard Albert Cartier , Vijay Narayanan
发明人： Bruce B. Doris , Charlotte DeWan Adams , Eduard Albert Cartier , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/28176 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/6653 , H01L29/6656
摘要： A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a liner without nitride portions. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have their threshold values set independently from one another.
摘要翻译：公开了一种CMOS结构，其中第一类型FET包含衬里，该衬垫具有氧化物和氮化物部分。氮化物部分形成衬套的边缘部分。这些氮化物部分能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种类型的FET器件具有没有氮化物部分的衬垫。结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有彼此独立设置的其阈值。

95. 发明申请

US20080258198A1 STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS 审中-公开
标题翻译：用于CMOS的基于氧化铝的硅晶体管中的平坦电压稳压和阈值电压稳定
公开(公告)号：US20080258198A1
公开(公告)日：2008-10-23
申请号：US12166690
申请日：2008-07-02
申请人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/76
CPC分类号： H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/517
摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising: a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.
摘要翻译：本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。具体地说，本发明提供了一种金属叠层，包括：铪基电介质; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

96. 发明申请

US20080249650A1 METHOD FOR COMPOSITION CONTROL OF A METAL COMPOUND FILM 失效
标题翻译：金属化合物膜的组成控制方法
公开(公告)号：US20080249650A1
公开(公告)日：2008-10-09
申请号：US11696507
申请日：2007-04-04
申请人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： G06F19/00 , G01N21/00
CPC分类号： G01N21/8422 , G01N21/59 , H01L22/12 , H01L22/20
摘要： Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.
摘要翻译：使用消光系数k的测量来有效且迅速地在线监测和/或控制金属膜组合物。消光系数对金属化合物的组成的依赖性的特征在于测量一系列具有不同组成的金属化合物的消光系数。然后将监测金属膜沉积在晶片上。测量晶片上的膜的消光系数k并提取膜组成参数。如果k在规范中，则可以继续进行晶片处理，或者可以从k的测量值中提取所需的胶片组成变化，并且建立k的关于对于超出规格k值的胶片的组成的依赖性。

97. 发明授权

US07432567B2 Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：具有至少一个栅极金属和双栅极电介质的金属栅极CMOS
公开(公告)号：US07432567B2
公开(公告)日：2008-10-07
申请号：US11320330
申请日：2005-12-28
申请人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Bruce B. Doris , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L31/119
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

98. 发明授权

US07432550B2 Semiconductor structure including mixed rare earth oxide formed on silicon 有权
标题翻译：包括在硅上形成的混合稀土氧化物的半导体结构
公开(公告)号：US07432550B2
公开(公告)日：2008-10-07
申请号：US10998840
申请日：2004-11-30
申请人： Nestor Alexander Bojarczuk, Jr. , Douglas Andrew Buchanan , Supratik Guha , Vijay Narayanan , Lars-Ake Ragnarsson
发明人： Nestor Alexander Bojarczuk, Jr. , Douglas Andrew Buchanan , Supratik Guha , Vijay Narayanan , Lars-Ake Ragnarsson
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/06 , H01L31/0328
CPC分类号： H01L21/02192 , B82Y10/00 , B82Y30/00 , H01L21/02293 , H01L21/31604
摘要： A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.
摘要翻译：形成半导体结构的方法（和结果）包括在硅上形成混合的稀土氧化物。混合的稀土氧化物与硅晶格匹配。

99. 发明申请

US20080203485A1 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法
公开(公告)号：US20080203485A1
公开(公告)日：2008-08-28
申请号：US11680108
申请日：2007-02-28
申请人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
发明人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

100. 发明申请

US20080189279A1 FAST ACCURATE FUZZY MATCHING 有权
标题翻译：快速精确匹配
公开(公告)号：US20080189279A1
公开(公告)日：2008-08-07
申请号：US11762672
申请日：2007-06-13
申请人： Uwe MAYER , Vijay Narayanan , Matthias Blume
发明人： Uwe MAYER , Vijay Narayanan , Matthias Blume
IPC分类号： G06F7/06
CPC分类号： G06F17/30542
摘要： A computer-implemented technique for fuzzy matching. This works quickly yet accurately to determine if a given computer-readable record is represented, by exact match or pretty close match, in a large collection of computer-readable records. Further tools may be provided to assess the character of the match.
摘要翻译：一种用于模糊匹配的计算机实现技术。这可以快速而准确地确定，以确定给定的计算机可读记录是通过精确匹配或非常接近的匹配来表示的，这些记录在大量的计算机可读记录集中。可以提供进一步的工具来评估比赛的特征。

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