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91. 发明申请

US20060067452A1 Clock and data recovery circuit 审中-公开
标题翻译：时钟和数据恢复电路
公开(公告)号：US20060067452A1
公开(公告)日：2006-03-30
申请号：US10948697
申请日：2004-09-24
申请人： Jianping Xu , Fabrice Paillet , Peter Hazucha , Tanay Karnik
发明人： Jianping Xu , Fabrice Paillet , Peter Hazucha , Tanay Karnik
IPC分类号： H03D3/24
CPC分类号： H03L7/091 , H04J3/0685 , H04L7/0079 , H04L7/033
摘要： A clock and data recovery circuit is provided that includes a phase/frequency detector to receive input data and multiphase clock signals. The phase/frequency detector including a first set of flip-flop circuits each to sample the input data at one of the multiphase clock signals and each to output a sampled data, and a second set of flip-flop circuits to retime the sampled data based on a similar clock signal applied to each of the second set of flip-flop circuits.
摘要翻译：提供了一种时钟和数据恢复电路，其包括用于接收输入数据和多相时钟信号的相位/频率检测器。相位/频率检测器包括第一组触发器电路，每个触发器电路各自以多相时钟信号中的一个采样输入数据，并且每个触发器电路各自输出采样数据;以及第二组触发器电路，用于基于采样数据进行加权在施加到每个第二组触发器电路的类似时钟信号上。

92. 发明申请

US20060066462A1 Single to dual non-overlapping converter 有权
标题翻译：单对双重非重叠转换器
公开(公告)号：US20060066462A1
公开(公告)日：2006-03-30
申请号：US10954127
申请日：2004-09-29
申请人： Fabrice Paillet , Tanay Karnik
发明人： Fabrice Paillet , Tanay Karnik
IPC分类号： H03M3/00
CPC分类号： H03K5/133 , H03K5/1515 , H03K2005/00202
摘要： A converter includes an input circuit to receive a single-ended input signal to generate a number of control signals. The control signals have a delay different from one another relative to the single-ended input signal. The converter also includes a first output circuit and a second output circuit. The first output circuit responds to the control signals to generate a first output signal. The second output circuit responds to the control signals to generate a second output signal. The first and second output signals are non-overlapping and form a complimentary signal pair.
摘要翻译： A转换器包括用于接收单端输入信号以产生多个控制信号的输入电路。控制信号相对于单端输入信号具有彼此不同的延迟。转换器还包括第一输出电路和第二输出电路。第一输出电路响应控制信号以产生第一输出信号。第二输出电路响应控制信号以产生第二输出信号。第一和第二输出信号是不重叠的，并形成一个互补信号对。

93. 发明授权

US06924510B2 Silicon and silicon/germanium light-emitting device, methods and systems 失效
标题翻译：硅和硅/锗发光器件，方法和系统
公开(公告)号：US06924510B2
公开(公告)日：2005-08-02
申请号：US10140255
申请日：2002-05-06
申请人： Donald S. Gardner , Tanay Karnik , Jianping Xu , Shekhar Y. Borkar
发明人： Donald S. Gardner , Tanay Karnik , Jianping Xu , Shekhar Y. Borkar
IPC分类号： G02B6/12 , G02B6/122 , G02B6/13 , G02B6/138 , G02B6/42 , G02B6/43 , H01L31/173 , H01L33/00 , H01L33/34 , H01L29/26
CPC分类号： H01L33/34 , G02B6/12004 , G02B6/1221 , G02B6/13 , G02B6/138 , G02B6/42 , G02B6/4214 , G02B6/4228 , G02B6/43 , G02B2006/12121 , H01L31/173
摘要： A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.
摘要翻译：公开了一种基于发光装置的发光装置和光通信系统。发光装置形成在浮区衬底中。发光装置在基板下表面上包括反射层，并且在上表面上包括间隔开的掺杂区域。掺杂区域之间的上表面的部分被纹理化并且任选地被抗反射涂层覆盖以增强发光。取决于抗反射涂层和反射层的反射率，发光器件可以作为激光器或发光二极管工作。

94. 发明申请

US20050156704A1 Magnetic material for transformers and/or inductors 有权
标题翻译：用于变压器和/或电感器的磁性材料
公开(公告)号：US20050156704A1
公开(公告)日：2005-07-21
申请号：US10760591
申请日：2004-01-21
申请人： Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
发明人： Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号： H01F10/13 , H01F10/187 , H01F17/00 , H01F27/28
CPC分类号： H01F17/0006 , H01F10/132 , H01F10/187 , H01F10/265 , H01F2017/0053
摘要： A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.
摘要翻译：提供一种变压器，其包括多个金属线和围绕多条金属线设置的磁性材料。磁性材料可以包括减少在磁性材料中流动的涡流的结构。该结构可以是垂直于金属线延伸的多个槽。该结构也可以是层叠结构。

95. 发明申请

US20050134347A1 Soft-error rate hardened pulsed latch 失效
标题翻译：软错误率硬化脉冲锁存器
公开(公告)号：US20050134347A1
公开(公告)日：2005-06-23
申请号：US10741560
申请日：2003-12-19
申请人： Stefan Rusu , Peter Hazucha , Tanay Karnik
发明人： Stefan Rusu , Peter Hazucha , Tanay Karnik
IPC分类号： H03K3/037
CPC分类号： H03K3/0375
摘要： A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.
摘要翻译：锁存器包括存储单元，转移单元，反转单元和输出单元。存储器单元包括多个存储节点。传送单元经由多个数据路径将数据从数据输入节点传送到存储节点。每个数据路径包括由脉冲控制的通过元件。在将数据从数据输入节点传送到至少一个存储节点之前，反转单元将数据反转。输出单元将数据从存储器单元输出到锁存输出节点。存储器单元，转移单元，反转单元和锁存器的输出单元形成具有减少元件数量并降低功耗的软错误率硬化锁存结构。

96. 发明申请

US20050069070A1 High-speed data sampler for optical interconnect 有权
标题翻译：用于光互连的高速数据采样器
公开(公告)号：US20050069070A1
公开(公告)日：2005-03-31
申请号：US10673218
申请日：2003-09-30
申请人： Fabrice Paillet , Tanay Karnik , Jianping Xu
发明人： Fabrice Paillet , Tanay Karnik , Jianping Xu
IPC分类号： H03L7/081 , H04L7/00
CPC分类号： H04L7/0079 , H03L7/0812 , H04L7/0008
摘要： A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are preferably based on a predetermined fraction of a data rate frequency of the data stream, and sampling is performed based on predetermined combinations of the clock signals. While the system and method is suitable for sampling data transmitted for a wide variety of data rates, the system and method is especially well-suited to sampling at data transmitted at high rates, for example, equal to or greater than 20 Gb/s.
摘要翻译：用于对数据流进行采样的系统和方法产生具有相等间隔相位的多个时钟信号，然后使用时钟信号对数据流进行采样。时钟相位优选地基于数据流的数据速率频率的预定分数，并且基于时钟信号的预定组合来执行采样。虽然系统和方法适合于为各种数据速率传输的数据采样，但是该系统和方法特别适合于以高速率传输的数据进行采样，例如等于或大于20Gb / s。

97. 发明授权

US06737924B1 Differential, double feedback CMOS transimpedance amplifier with noise tolerance 失效
标题翻译：差分双反馈CMOS跨阻抗放大器，具有噪声容限
公开(公告)号：US06737924B1
公开(公告)日：2004-05-18
申请号：US10317709
申请日：2002-12-11
申请人： Fabrice Paillet , Tanay Karnik
发明人： Fabrice Paillet , Tanay Karnik
IPC分类号： H03F308
CPC分类号： H03F1/083 , H03F1/342 , H03F3/082 , H03F3/265
摘要： A transimpedance amplifier having a first input port to connect to a signal source having an output impedance, and a second input port loaded by an impedance matched to the output impedance of the signal source, the amplifier comprising three stage pairs. The first stage pair comprises two inverting amplifiers, each employing negative feedback. The second stage pair comprises two inverting amplifiers with cross-coupled negative feedback. The third stage pair is similar in structure to the first stage pair. The inverter amplifiers in the third stage pair provide the differential voltage.
摘要翻译：一种跨阻放大器，具有连接到具有输出阻抗的信号源的第一输入端口和由与信号源的输出阻抗匹配的阻抗加载的第二输入端口，该放大器包括三个级对。第一级对包括两个反相放大器，每个反相放大器采用负反馈。第二级对包括具有交叉耦合负反馈的两个反相放大器。第三级对在结构上与第一级对相似。第三级对中的反相放大器提供差分电压。

98. 发明授权

US06639472B2 High bandwidth, low power, single stage cascode transimpedance amplifier for short haul optical links 有权
标题翻译：用于短距离光链路的高带宽，低功耗，单级共源共栅跨阻放大器
公开(公告)号：US06639472B2
公开(公告)日：2003-10-28
申请号：US10107679
申请日：2002-03-26
申请人： Timothy M. Wilson , Tanay Karnik , Luiz M. Franca-Neto
发明人： Timothy M. Wilson , Tanay Karnik , Luiz M. Franca-Neto
IPC分类号： H03F308
CPC分类号： H03F3/082
摘要： A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.
摘要翻译：用于短距离光链路的高带宽，单级，低功率共源共栅跨阻放大器。在一个实施例中，输入信号被馈送到共栅极pMOSFET的源极中，输出信号在公共栅极pMOSFET的漏极处获取，并且偏置电流由偏置在其三极管区域中的pMOSFET和nMOSFET提供。

99. 发明授权

US06504412B1 Storage element with switched capacitor 失效
标题翻译：带开关电容器的存储元件
公开(公告)号：US06504412B1
公开(公告)日：2003-01-07
申请号：US09663750
申请日：2000-09-15
申请人： Sriram R. Vangal , Tanay Karnik
发明人： Sriram R. Vangal , Tanay Karnik
IPC分类号： G06F764
CPC分类号： H03K3/013 , H03K3/356191
摘要： A latch includes a pair of inverters cross-coupled between a storage node and a feedback node. A capacitor is conditionally coupled to the feedback node through a pass gate such that the capacitor is coupled to the feedback node when the latch holds data and is not coupled to the feedback node when the latch is loading. The capacitor reduces the latch's susceptibility to soft errors when holding data, and does not appreciably slow the latch when data is loading. The capacitor is implemented using the gate capacitance of complementary transistors. A flip-flop includes cascaded latches, one or more of which have a switched capacitor on a feedback node.
摘要翻译：锁存器包括交叉耦合在存储节点和反馈节点之间的一对反相器。电容器有条件地通过传递门耦合到反馈节点，使得当锁存器保持数据时，电容器耦合到反馈节点，并且当锁存器被加载时，电容器不耦合到反馈节点。当保存数据时，电容会降低锁存器对软错误的敏感性，并且在数据加载时不会明显减慢锁存器的速度。使用互补晶体管的栅极电容来实现电容器。触发器包括级联锁存器，其中一个或多个锁存器在反馈节点上具有开关电容器。

100. 发明申请

US20220012570A1 BAYESIAN COMPUTE UNIT WITH RECONFIGURABLE SAMPLER AND METHODS AND APPARATUS TO OPERATE THE SAME 有权
公开(公告)号：US20220012570A1
公开(公告)日：2022-01-13
申请号：US17483382
申请日：2021-09-23
申请人： Srivatsa Rs , Indranil Chakraborty , Ranganath Krishnan , Uday A Korat , Muluken Hailesellasie , Jainaveen Sundaram Priya , Deepak Dasalukunte , Dileep Kurian , Tanay Karnik
发明人： Srivatsa Rs , Indranil Chakraborty , Ranganath Krishnan , Uday A Korat , Muluken Hailesellasie , Jainaveen Sundaram Priya , Deepak Dasalukunte , Dileep Kurian , Tanay Karnik
IPC分类号： G06N3/04 , G06N3/063 , G06F7/58 , G06F9/30
摘要： Methods, apparatus, systems, and articles of manufacture providing a Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same are disclosed. An example apparatus includes a processor element to generate (a) a first element by applying a mean value to an activation and (b) a second element by applying a variance value to a square of the activation, the mean value and the variance value corresponding to a single probability distribution; a programmable sampling unit to: generate a pseudo random number; and generate an output based on the pseudo random number, the first element, and the second element, wherein the output corresponds to the single probability distribution; and output memory to store the output.

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