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91. 发明授权

US09426098B2 Synchronizing out-of-sync elements in a distributed fibre channel forwarder 有权
标题翻译：在分布式光纤通道转发器中同步不同步的元素
公开(公告)号：US09426098B2
公开(公告)日：2016-08-23
申请号：US14264681
申请日：2014-04-29
申请人： International Business Machines Corporation
发明人： Henry J. May , Christoph Raisch , Stefan Roscher , Daniel Sentler , Bharath B. Somayaji , Sudheer R. Yelanduru
IPC分类号： H04L29/06 , H04L12/931 , H04L12/54 , H04L12/935 , H04L7/00 , H04J3/06 , H04L12/24 , H04L12/939
CPC分类号： H04L49/357 , H04J3/0697 , H04L7/0016 , H04L12/56 , H04L41/0668 , H04L41/0803 , H04L49/3009 , H04L49/557
摘要： Techniques are provided for synchronizing, in a distributed Fiber Channel fabric or a distributed FCoE fabric in which FC frames are encapsulated in Ethernet frames, a controlling FCoE forwarder (cFCF) with the FCoE data-plane forwarder (FDF). The operation includes entering a recovery mode at the FDF. The FDF is modified based on a route distribution message provided by the cFCF which includes fabric-provided MAC addresses (FPMAs). The FDF notifies the cFCF of differences between the FPMAs supplied by the route distribution message with the FPMAs known by the FDF. The FDF leaves the recovery mode and sends an acknowledgement to the cFCF.
摘要翻译：提供了技术，用于在FCoE数据平面转发器（FDF）中的分布式光纤通道结构或其中FC帧被封装在以太网帧中的分布式FCoE架构中同步控制FCoE转发器（cFCF）。操作包括在FDF中进入恢复模式。基于由包括结构提供的MAC地址（FPMA）的cFCF提供的路由分发消息来修改FDF。 FDF将通过路由分发消息提供的FPMA与FDF已知的FPMA之间的差异通知给cFCF。 FDF离开恢复模式并向cFCF发送确认。

92. 发明授权

US09230110B2 Accessing privileged objects in a server environment 有权
标题翻译：访问服务器环境中的特权对象
公开(公告)号：US09230110B2
公开(公告)日：2016-01-05
申请号：US14064817
申请日：2013-10-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Utz Bacher , Christoph Raisch , Einar Lueck , Frank Blaschka
IPC分类号： G06F7/04 , G06F15/16 , G06F17/30 , H04L29/06 , G06F21/57 , G06F21/74 , G06F9/46
CPC分类号： H04L63/102 , G06F9/468 , G06F21/57 , G06F21/74 , G06F2221/2145
摘要： Accessing privileged objects in a server environment. A privileged object is associated with an application comprising at least one process resource and a corresponding semi-privileged instruction. The association is filed in an entity of an operating system kernel. A central processing unit (CPU) performs an authorization check if the semi-privileged instruction is issued and attempts to access the privileged object. The CPU executes the semi-privileged instruction and grants access to the privileged object if the operating system kernel has issued the semi-privileged instruction; or accesses the entity if a process resource of the application has issued the semi-privileged instruction to determine authorization of the process resource to access the privileged object. Upon positive authorization the CPU executes the semi-privileged instruction and grants access to the privileged object, and upon authorization failure denies execution of the semi-privileged instruction and performs a corresponding authorization check failure handling.
摘要翻译：访问服务器环境中的特权对象。特权对象与包括至少一个进程资源和相应的半特权指令的应用程序相关联。该协会提交在操作系统内核的实体中。中央处理单元（CPU）执行授权检查，如果发出半特权指令并尝试访问特权对象。如果操作系统内核发出了半特权指令，CPU将执行半特权指令并授予对特权对象的访问权限; 或者如果应用的进程资源已经发出半特权指令来确定进程资源访问特权对象的授权，则访问该实体。在正式授权下，CPU执行半特权指令并授予对特权对象的访问权限，并且在授权失败时，拒绝执行半特权指令并执行相应的授权检查失败处理。

93. 发明申请

US20140092912A1 FIBRE CHANNEL OVER ETHERNET SWITCH IMPLICIT LOGOUT 有权
标题翻译：光纤通道以太网交换机隐藏式注销
公开(公告)号：US20140092912A1
公开(公告)日：2014-04-03
申请号：US13630331
申请日：2012-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Roger G. Hathorn , Henry J. May , Christoph Raisch , Louis W. Ricci , Daniel Sentler
IPC分类号： H04L12/931
CPC分类号： H04L49/351
摘要： A process for an implicit logout of links to a fibre channel over Ethernet switch includes receiving, at a second switch, a first message from a first switch. The first message indicates an implicit link logout event on one of two or more links between the first switch and a node. Also, the process includes transmitting a second message from the second switch. The second message indicates zoning information for all of the two or more links between the first switch and the node.
摘要翻译：用于通过以太网交换机对光纤通道的链接的隐式注销的过程包括在第二交换机处从第一交换机接收第一消息。第一个消息表示第一个交换机和一个节点之间的两个或多个链路之一上的隐式链接注销事件。而且，该过程包括从第二交换机发送第二消息。第二消息指示第一交换机和节点之间的所有两个或多个链路的分区信息。

94. 发明授权

US11829790B2 Directed interrupt virtualization with fallback 有权
公开(公告)号：US11829790B2
公开(公告)日：2023-11-28
申请号：US17506368
申请日：2021-10-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christoph Raisch , Marco Kraemer , Donald William Schmidt , Bernd Nerz , Peter Dana Driever
IPC分类号： G06F9/455 , G06F9/48 , G06F9/50 , G06F9/54 , G06F13/24
CPC分类号： G06F9/45545 , G06F9/4812 , G06F9/4881 , G06F9/5027 , G06F9/542 , G06F13/24
摘要： A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

95. 发明公开

US20230195653A1 SECURE COMMUNICATION OF VIRTUAL MACHINE ENCRYPTED MEMORY 审中-公开
公开(公告)号：US20230195653A1
公开(公告)日：2023-06-22
申请号：US17644651
申请日：2021-12-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hubertus Franke , Christoph Raisch , Bulent Abali , Marco Kraemer
IPC分类号： G06F12/14 , G06F12/1045 , G06F13/16 , G06F9/455
CPC分类号： G06F12/1408 , G06F12/1433 , G06F12/145 , G06F12/1466 , G06F12/1054 , G06F12/1063 , G06F13/1668 , G06F13/161 , G06F9/45558 , G06F2009/45583
摘要： An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

96. 发明授权

US11269794B2 Directed interrupt for multilevel virtualization with interrupt table 有权
公开(公告)号：US11269794B2
公开(公告)日：2022-03-08
申请号：US16789556
申请日：2020-02-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christoph Raisch , Marco Kraemer , Donald William Schmidt , Bernd Nerz , Peter Dana Driever
IPC分类号： G06F13/24 , G06F9/455 , G06F9/48 , G06F9/50 , G06F12/1081
摘要： An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

97. 发明授权

US11243791B2 Directed interrupt virtualization with fallback 有权
公开(公告)号：US11243791B2
公开(公告)日：2022-02-08
申请号：US16789600
申请日：2020-02-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christoph Raisch , Marco Kraemer , Donald William Schmidt , Bernd Nerz , Peter Dana Driever
IPC分类号： G06F9/455 , G06F9/48 , G06F9/50 , G06F9/54 , G06F13/24
摘要： An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

98. 发明申请

US20220004412A1 DIRECTED INTERRUPT VIRTUALIZATION WITH RUNNING INDICATOR 有权
公开(公告)号：US20220004412A1
公开(公告)日：2022-01-06
申请号：US17482514
申请日：2021-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marco Kraemer , Christoph Raisch , Bernd Nerz , Donald William Schmidt , Matthias Klein , Sascha Junghans , Peter Dana Driever
IPC分类号： G06F9/455 , G06F9/48 , G06F9/50 , G06F9/54
摘要： An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

99. 发明授权

US11188379B2 Thermal capacity optimization for maximized single core performance 有权
公开(公告)号：US11188379B2
公开(公告)日：2021-11-30
申请号：US16137643
申请日：2018-09-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marco Kraemer , Matteo Michel , Carsten Otte , Christoph Raisch
IPC分类号： G06F9/48 , G06F1/3228
摘要： Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.

100. 发明授权

US11163566B2 Handling an input/output store instruction 有权
公开(公告)号：US11163566B2
公开(公告)日：2021-11-02
申请号：US16775663
申请日：2020-01-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christoph Raisch , Marco Kraemer , Frank Siegfried Lehnert , Matthias Klein , Jonathan D. Bradbury , Christian Jacobi , Brenton Belmar , Peter Dana Driever
IPC分类号： G06F9/30 , G06F9/451 , G06F9/38 , G06F9/4401 , G06F11/07 , G06F9/54
摘要： An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

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