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91. 发明授权

US07528630B2 High speed flip-flop 失效
标题翻译：高速触发器
公开(公告)号：US07528630B2
公开(公告)日：2009-05-05
申请号：US11970629
申请日：2008-01-08
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K19/00
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.
摘要翻译：触发器电路包括：预充电电路，其响应于第一脉冲信号对第一电路节点进行预充电;以及估计电路，其接收输入信号和第二脉冲信号。在激活第二脉冲信号时，估计电路响应于输入信号从第一节点放电电压。第一脉冲信号与时钟信号同步，第二脉冲信号从第一脉冲信号延迟。

92. 发明授权

US07504871B2 Flip-flops and electronic digital circuits including the same 有权
标题翻译：触发器和包括其的电子数字电路
公开(公告)号：US07504871B2
公开(公告)日：2009-03-17
申请号：US11819388
申请日：2007-06-27
申请人： Min-Su Kim , Bai-Sun Kong
发明人： Min-Su Kim , Bai-Sun Kong
IPC分类号： H03K3/00
CPC分类号： H03K3/356121 , H03K3/356147 , H03K3/356191
摘要： A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.
摘要翻译：触发器包括接收时钟信号和第一信号的第一电路，并且当时钟信号进入有效电平时，将第一和第二输出信号转换到第一电平，第二电路将第一信号转换到第一电平在第一和第二输出信号进入第一级之后。当时钟信号处于有效电平并且第一信号处于第一电平时，第一电路将第一和第二输入信号从第一和第二输入端传送到第一和第二输出端。

93. 发明申请

US20080226222A1 OPTO-ELECTRIC BUS MODULE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：光电总线模块及其制造方法
公开(公告)号：US20080226222A1
公开(公告)日：2008-09-18
申请号：US12049261
申请日：2008-03-14
申请人： Jin Tae Kim , Suntak Park , Jung Jin Ju , Seung Koo Park , Min-Su Kim , Myung Hyun Lee
发明人： Jin Tae Kim , Suntak Park , Jung Jin Ju , Seung Koo Park , Min-Su Kim , Myung Hyun Lee
IPC分类号： G02B6/12 , B05D5/06
CPC分类号： G02B6/423 , G02B6/4214 , G02B6/43
摘要： Provided are an opto-electric bus module and a method of manufacturing the opto-electric bus module. The opto-electric bus module includes an opto-electric interconnection unit where a concave-shaped micro structure is formed on a lower surface of a polymer structure and an optical bench where a convex-shaped micro structure is formed in a position corresponding to the concave-shaped micro structure, at least one second electric interconnection for electric connection with a semiconductor chip is formed, and the semiconductor chip and an opto-electric device can be mounted. Thus, automatic, efficient, high-speed, and high-integration optical communication and electric communication between multi-chips can be completed at the same time by using the opto-bus module which provides low-speed electric communication while manually maintaining solid optical coupling.
摘要翻译：提供了一种光电总线模块和一种制造光电总线模块的方法。光电总线模块包括光电互连单元，其中在聚合物结构的下表面上形成凹形微结构，在其上形成凸形微结构在与凹部对应的位置形成微型结构，形成至少一个用于与半导体芯片电连接的第二电互连，并且可以安装半导体芯片和光电装置。因此，可以通过使用提供低速电气通信的光总线模块同时完成多芯片之间的自动，高效，高集成度的光通信和电通信，同时手动保持固体光耦合。

94. 发明授权

US07358786B2 Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop 有权
标题翻译：控制信号发生器，锁存电路，触发器和用于控制触发器操作的方法
公开(公告)号：US07358786B2
公开(公告)日：2008-04-15
申请号：US11128294
申请日：2005-05-13
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K3/356
CPC分类号： G01R31/318575 , G01R31/318552 , H03K3/0375
摘要： A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulses based on a scan enable signal being received in a first state and on a received clock signal, and may generate at least two internal clock signals based on the received clock signal, and based on the scan enable signal being received in a second state. The latch circuit may latch a received input signal based on the at least two pulses and may latch a received scan input signal based on the at least two internal clock signals.
摘要翻译：可以配置用于控制触发器中的操作的控制信号发生器，锁存电路，触发器和方法，以有效地执行触发器中的锁存和扫描操作。控制信号发生器可以基于在第一状态和接收的时钟信号中接收到的扫描使能信号来生成至少两个脉冲，并且可以基于接收到的时钟信号，并且基于扫描来生成至少两个内部时钟信号使能信号在第二状态下被接收。锁存电路可以基于至少两个脉冲来锁存接收到的输入信号，并且可以基于至少两个内部时钟信号来锁存接收到的扫描输入信号。

95. 发明申请

US20070080734A1 Pulse-based flip-flop 审中-公开
公开(公告)号：US20070080734A1
公开(公告)日：2007-04-12
申请号：US11635015
申请日：2006-12-07
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K3/00
CPC分类号： H03K5/151 , H03K3/037 , H03K5/135 , H03K5/1534
摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

96. 发明申请

US20060097754A1 Gated clock logic circuit 有权
标题翻译：门控时钟逻辑电路
公开(公告)号：US20060097754A1
公开(公告)日：2006-05-11
申请号：US11266659
申请日：2005-11-02
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K19/096
CPC分类号： G06F1/04 , G06F1/3237 , H03K3/012 , H03K3/356121 , H03K5/135 , Y02D10/128
摘要： A gated clock logic circuit includes a pulse generator and a precharged latch. The pulse generator generates a pulse signal in response to a clock signal, and the precharged latch generates a gated clock signal in response to the clock signal, the pulse signal, and a control signal.
摘要翻译：门控时钟逻辑电路包括脉冲发生器和预充电锁存器。脉冲发生器响应于时钟信号产生脉冲信号，并且预充电锁存器响应于时钟信号，脉冲信号和控制信号产生门控时钟信号。

97. 发明申请

US20050116756A1 Pulse-based flip-flop 有权
标题翻译：基于脉冲的触发器
公开(公告)号：US20050116756A1
公开(公告)日：2005-06-02
申请号：US10997958
申请日：2004-11-29
申请人： Min-Su Kim
发明人： Min-Su Kim
IPC分类号： H03K3/037 , H03K3/356 , H03K5/13 , H03K5/135 , H03K5/151 , H03K5/1534
CPC分类号： H03K5/151 , H03K3/037 , H03K5/135 , H03K5/1534
摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.
摘要翻译：基于脉冲的触发器，其锁存数据输入信号，以响应于时钟信号将数据输入信号转换成数据输出信号。基于脉冲的触发器包括响应于第一时钟脉冲信号和第二时钟脉冲信号而锁存数据输入信号的锁存器和包括与非门，可变延迟和第一反相器的脉冲发生器，所述脉冲发生器接收时钟信号以产生第一时钟脉冲信号和第二时钟脉冲信号。 NAND门接收时钟信号和可变延迟的输出信号，并输出第二时钟脉冲信号。第一反相器接收第一时钟脉冲信号并输出第二时钟脉冲信号。可变延迟接收时钟信号和第二时钟脉冲，并且可变延迟的输出信号反馈到NAND门。

98. 发明授权

US5532900A Semiconductor arrester 失效
标题翻译：半导体避雷器
公开(公告)号：US5532900A
公开(公告)日：1996-07-02
申请号：US386907
申请日：1995-02-08
申请人： Min-Su Kim , Itsunari Hamada
发明人： Min-Su Kim , Itsunari Hamada
IPC分类号： H01C8/04 , H01B17/42 , H02H9/04 , H02H9/06
CPC分类号： H02H9/044 , H01L2224/32245 , H01L2924/1301
摘要： To enable the mounting of arrester in a small-sized package of a resin-sealed type for general use, such as a T0-92 package or a T0-220 package, by modifying the arrangement of diodes and thyristor there is provided: a diode-bridge thyristor type of semiconductor arrester, comprising: a pair of opposed metal plates (20, 21); a thyristor (T1) between the metal plates (20, 21); three pairs of diodes (D1, D2: D3, D4: D5, D6) between the metal plates (20, 21); and three leads (22, 23, 24), each provided between each pair of diodes.
摘要翻译：为了能够通过修改二极管和晶闸管的布置来将避雷器安装在通常用于树脂密封型的小型封装中，例如T0-92封装或T0-220封装，提供：二极管桥式晶闸管型半导体避雷器，包括：一对相对的金属板（20,21）; 金属板（20,21）之间的晶闸管（T1）; 金属板（20,21）之间的三对二极管（D1，D2：D3，D4：D5，D6）; 和三个引线（22,23,24），每个引线（22,23,24）设置在每对二极管之间。

99. 发明授权

US09201533B2 Substrate for in-cell type touch sensor liquid crystal display device and method of fabricating the same 有权
标题翻译：晶胞型触摸传感器液晶显示装置用基板及其制造方法
公开(公告)号：US09201533B2
公开(公告)日：2015-12-01
申请号：US13333053
申请日：2011-12-21
申请人： Min-Su Kim , Myeong-Sik Lee
发明人： Min-Su Kim , Myeong-Sik Lee
IPC分类号： G06F3/041 , G06F3/044 , G02F1/1333 , G02F1/1362 , G02F1/1343
CPC分类号： G02F1/13338 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134372 , G02F2001/136295 , G06F3/0412 , G06F3/044 , G06F3/047 , G06F2203/04103 , H01L27/1274
摘要： An array substrate for an in-cell type touch sensor liquid crystal display device includes: a substrate; a gate line and a data line on the substrate; a thin film transistor connected to the gate line and the data line; a first passivation layer on the thin film transistor; a common electrode on the first passivation layer; an etching preventing pattern covering the drain contact hole; an x sensing line and a y sensing line on the common electrode; a second passivation layer on the x sensing line and the y sensing line; and a pixel electrode on the second passivation layer.
摘要翻译：一种用于单元式触摸传感器液晶显示装置的阵列基板，包括：基板; 基板上的栅极线和数据线; 连接到栅极线和数据线的薄膜晶体管; 薄膜晶体管上的第一钝化层; 在第一钝化层上的公共电极; 覆盖漏极接触孔的防蚀图案; 公共电极上的x感测线和y感测线; x感测线和y感测线上的第二钝化层; 以及第二钝化层上的像素电极。

100. 发明授权

US09160317B2 Semiconductor circuit and method of operating the same 有权
标题翻译：半导体电路及其操作方法
公开(公告)号：US09160317B2
公开(公告)日：2015-10-13
申请号：US13844242
申请日：2013-03-15
申请人： Rahul Singh , Min-Su Kim
发明人： Rahul Singh , Min-Su Kim
IPC分类号： H03K3/00 , H03K3/356
CPC分类号： H03K3/356121
摘要： Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses.
摘要翻译：提供半导体电路及其操作方法。该半导体电路包括：第一脉冲发生电路，其能够进入时钟信号的上升沿，并被配置为产生第一读取脉冲，第二脉冲发生电路使能到时钟信号的上升沿并被配置为产生独立的第二读取脉冲所述动态下拉阶段被配置为至少基于输入信号和所述第一和第二读取脉冲的数据值来开发第一动态节点的电压电平;以及动态上拉阶段，被配置为至少基于输入信号和第一和第二读取脉冲的数据值来开发第二动态节点的电压电平。

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