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91. 发明申请

US20050249694A1 Methods and articles for maintaining hydantoinylated polymers in a biocidally active state 失效
标题翻译：维持乙酰乙酰化聚合物处于生物活性状态的方法和制品
公开(公告)号：US20050249694A1
公开(公告)日：2005-11-10
申请号：US11180280
申请日：2005-07-12
申请人： Michael Bridges , Hiroyuki Kawai , Tay-Yuan Chen , Everett Nichols , Jeffrey Williams , Steven McClure , Jerry Wetherbee
发明人： Michael Bridges , Hiroyuki Kawai , Tay-Yuan Chen , Everett Nichols , Jeffrey Williams , Steven McClure , Jerry Wetherbee
IPC分类号： A01N59/00 , A61K31/785 , C01B11/00 , C02F1/28 , C02F1/68 , C02F1/76 , C09K3/00
CPC分类号： C01B11/00 , A01N59/00 , C02F1/001 , C02F1/283 , C02F1/688 , C02F1/76 , C02F1/766 , A01N25/34 , A01N25/10 , A01N25/08 , A01N2300/00
摘要： A composition and the method for sustaining the biocidal activity of chlorinated polystyrene hydantoin beads. The method comprises supplying a continuous low level halogen concentration to the chlorinated polystyrene hydantoin beads in the water to be treated that flows in contact with the chlorinated polystyrene hydantoin beads, resulting in treated water suitable for drinking.
摘要翻译：维持氯化聚苯乙烯乙内酰脲珠粒的杀生物活性的组合物和方法。该方法包括向与氯化聚苯乙烯乙内酰脲珠接触的待处理水中的氯化聚苯乙烯乙内酰脲珠提供连续低浓度卤素浓度，得到适于饮用的处理水。

92. 发明授权

US06603481B1 Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权
标题翻译：能够并行执行输入/输出和高速几何计算处理的几何处理器
公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译：几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。

93. 发明授权

US06272582B1 PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device 失效
标题翻译：允许控制包括VGA设备的多个PCI代理的PCI-PCI桥
公开(公告)号：US06272582B1
公开(公告)日：2001-08-07
申请号：US09140317
申请日：1998-08-26
申请人： Robert Streitenberger , Hiroyuki Kawai
发明人： Robert Streitenberger , Hiroyuki Kawai
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： A PCI-PCI bridge is connected between a primary PCI bus and a secondary PCI bus, and includes a bridge for connecting the secondary PCI bus to the primary PCI bus. The bridge has a type “00” configuration header, and identifies, at the time of configuration, one of a plurality of PCI agents including a VGA device on the secondary PCI bus based on a value of a function number field of the configuration command from the device driver, and that the identified agent to execute configuration.
摘要翻译： PCI-PCI桥接器连接在主PCI总线和辅助PCI总线之间，并且包括用于将辅助PCI总线连接到主PCI总线的桥。该桥具有类型“00”配置头，并且在配置时，基于辅助PCI总线上的VGA设备，基于配置命令的功能号字段的值来识别配置时的多个PCI代理之一设备驱动程序，以及所识别的代理执行配置。

94. 发明授权

US6142026A Wheel information estimating apparatus 失效
标题翻译：车轮信息估计装置
公开(公告)号：US6142026A
公开(公告)日：2000-11-07
申请号：US458099
申请日：1995-06-01
申请人： Hideki Ohashi , Hiroyuki Kawai , Hiroyoshi Kojima , Takaji Umeno , Katsuhiro Asano , Toshiharu Naito , Nobuyoshi Onogi
发明人： Hideki Ohashi , Hiroyuki Kawai , Hiroyoshi Kojima , Takaji Umeno , Katsuhiro Asano , Toshiharu Naito , Nobuyoshi Onogi
IPC分类号： B60C23/06 , G01M15/00 , B60C23/00 , G01L17/00
CPC分类号： B60C23/062 , B60C23/061
摘要： A wheel information estimating apparatus, which includes: a detecting device for detecting a wheel motion state relating to a movement of a tired wheel of a motor vehicle; an estimating device for estimating wheel information relating to the tired wheel, on the basis of the wheel motion state detected by the detecting device; and a modifying device for modifying an element relating to estimation of the wheel information, so as to improve an accuracy of estimating the wheel information. The element to be modified is selected from a movement of a center of rotation of the tired wheel as viewed in a plane in which the wheel is rotated, a signal applied from the detecting device to the estimating device, and an internal parameter used by the estimating means for estimating the wheel information.
摘要翻译：一种车轮信息估计装置，包括：检测装置，用于检测与机动车辆的轮胎的运动有关的车轮运动状态; 基于由所述检测装置检测到的车轮运动状态来估计与所述轮胎相关的车轮信息的估计装置; 以及用于修改与车轮信息的估计有关的元件的修改装置，以便提高车轮信息的估计精度。要修改的元件选自在车轮旋转的平面中观察到的轮胎的旋转中心的运动，从检测装置施加到估计装置的信号，以及由用于估计车轮信息的估计装置。

95. 发明授权

US5848114A Computerized tomography system 失效
标题翻译：计算机断层摄影系统
公开(公告)号：US5848114A
公开(公告)日：1998-12-08
申请号：US821539
申请日：1997-03-21
申请人： Hiroyuki Kawai , Kensuke Sekihara , Nagaaki Ohyama , Masahiro Yamaguchi , Takashi Obi
发明人： Hiroyuki Kawai , Kensuke Sekihara , Nagaaki Ohyama , Masahiro Yamaguchi , Takashi Obi
IPC分类号： A61B6/03 , G06T11/00
CPC分类号： G06T11/003 , Y10S378/901
摘要： A computerized tomography system including an X-ray source for emitting X-rays in a cone-beam shape, a two-dimensional X-ray image acquirer which is arranged so as to face the X-ray source and acquires an image of an object by using the X-rays; and rotator for rotating the X-ray source and the two-dimensional x-ray image acquirer around the object, wherein a three-dimensional reconstructed image is formed from the projection images acquired by the two-dimensional X-ray image acquirer while rotating the rotator. An iterative reconstruction calculator for forming the three-dimensional reconstructed image from the projection images is provided. The three-dimensional reconstructed image without artifacts can be acquired from a small amount of projection data.
摘要翻译：包括用于发射锥形束X射线的X射线源的计算机断层摄影系统，被配置为面对X射线源并获取对象的图像的二维X射线图像获取器通过使用X射线; 旋转器，用于将X射线源和二维X射线图像获取器旋转到物体周围，其中由二维X射线图像获取器获取的投影图像形成三维重建图像，同时旋转旋转器提供了一种用于从投影图像形成三维重建图像的迭代重建计算器。可以从少量的投影数据获取无伪像的三维重建图像。

96. 发明授权

US5697016A Image forming apparatus operable in horizontal and vertical installations 失效
标题翻译：图像形成装置可在水平和垂直安装中操作
公开(公告)号：US5697016A
公开(公告)日：1997-12-09
申请号：US597248
申请日：1996-02-06
申请人： Kunihiro Kitsu , Kaneatsu Uchiyama , Nobuyuki Tanaka , Hiroyuki Kawai
发明人： Kunihiro Kitsu , Kaneatsu Uchiyama , Nobuyuki Tanaka , Hiroyuki Kawai
IPC分类号： G03G15/20 , G03G15/32 , G03G21/20
CPC分类号： G03G21/206 , G03G15/2017 , G03G15/2039 , G03G15/2064 , G03G15/32 , G03G21/203 , G03G2215/00012
摘要： Disclosed is an image forming apparatus for forming a toner image on a sheet both in a horizonal installation and in a vertical installation of the apparatus. The image forming apparatus is designed so that an air flow from a thermal fixing unit exerts no influence on an image forming operation of a photosensitive body and a temperature detection operation of the thermal fixing unit even when installed horizontally or vertically. This image forming apparatus therefore includes an exhaust duct for guiding a gas of an interior of the thermal fixing unit in an upper oblique direction from the thermal fixing unit to exhaust the interior Of the thermal fixing unit. The air flow from the thermal fixing unit does not therefore influence an image formation on the photosensitive body even when the apparatus is installed horizontally or vertically. This image forming apparatus also includes a temperature detector provided obliquely to a heat roller of the thermal fixing unit. The image forming apparatus further includes a plurality of temperature detectors each provided in a different position with respect to the heat roller of the thermal fixing unit. The image forming apparatus still further includes a temperature detector for detecting a temperature of the heat roller and a control circuit for controlling a fixing temperature of the heat roller by comparing a set temperature corresponding to an installing direction of the apparatus with a temperature detected by the temperature detector. The temperature of the heat roller can be therefore accurately controlled irrespective of the installing direction of the apparatus.
摘要翻译：公开了一种用于在水平安装和垂直安装中在片材上形成调色剂图像的图像形成装置。图像形成装置被设计成使得即使在水平或垂直安装时，来自热定影单元的空气流也不影响感光体的图像形成操作和热定影单元的温度检测操作。因此，该图像形成装置包括用于从热定影单元沿上倾斜方向引导热定影单元的内部的气体排出热定影单元的内部的排气管道。因此，即使装置水平或垂直安装，来自热定影单元的空气流也不影响感光体上的图像形成。该图像形成装置还包括倾斜于热定影单元的加热辊设置的温度检测器。图像形成装置还包括多个温度检测器，每个温度检测器设置在相对于热定影单元的加热辊的不同位置。图像形成装置还包括用于检测加热辊的温度的温度检测器和用于通过将与设备的安装方向相对应的设定温度与由该设备的安装方向相对应的温度进行比较来控制加热辊的定影温度的控制电路温度检测器因此，无论装置的安装方向如何，都可以精确地控制加热辊的温度。

97. 发明授权

US5673422A Semiconductor integrated circuit for processing image data 失效
标题翻译：用于处理图像数据的半导体集成电路
公开(公告)号：US5673422A
公开(公告)日：1997-09-30
申请号：US376618
申请日：1995-01-23
申请人： Hiroyuki Kawai , Yoshitsugu Inoue , Hisashi Nakamura
发明人： Hiroyuki Kawai , Yoshitsugu Inoue , Hisashi Nakamura
IPC分类号： G09G5/00 , G06F12/08 , G06T1/20 , G06T3/00 , G06T11/00 , G06T15/10 , G09G5/39 , G09G5/393 , G11C11/401 , G06F15/76
CPC分类号： G06T1/20 , G09G5/393
摘要： A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.
摘要翻译：帧缓冲存储器包括DRAM的主存储器，SRAM的高速缓冲存储器，用于传送256位数据的第一传输总线，例如主存储器和高速缓冲存储器之间的像素处理单元，用于执行根据从高速缓冲存储器提供的数据和外部应用数据的预定操作处理，用于将从高速缓存存储器提供的数据与外部应用数据进行比较的比较单元，用于将数据从高速缓冲存储器传送到像素处理单元的传输总线，以及比较单元，用于将结果数据从像素处理单元传送到高速缓冲存储器的传送总线，以及用于存储从主存储器读出的数据的串行存取存储器，并将所存储的数据串行地提供给外部世界。根据该结构，图形所需的alpha混合处理，光栅操作，Z比较处理等可以灵活地高速地进行。

98. 发明授权

US5657485A Program control operation to execute a loop processing not immediately following a loop instruction 失效
标题翻译：程序控制操作执行循环指令后不循环处理
公开(公告)号：US5657485A
公开(公告)日：1997-08-12
申请号：US509940
申请日：1995-08-01
申请人： Robert Streitenberger , Hiroyuki Kawai , Yoshitsugu Inoue
发明人： Robert Streitenberger , Hiroyuki Kawai , Yoshitsugu Inoue
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F9/30065
摘要： The present invention is directed to a program control unit which enables a program control to achieve an efficient loop processing which does not immediately follow a loop instruction and which contains a start address and end address. In the program control unit, the start address and end address of a loop processing are stored in a register (start) (7) and a register (end) (8), respectively, in synchronization with a clock t1. The stored data "start" of the register (7) and the stored data "end" of the register (8) are inputted to a comparator (12) and a comparator (11), respectively. The comparator (12) compares the output from a delay program counter (18) with the data "start", and sets a flag f start when the comparison result indicates agreement and otherwise resets it. The comparator (11) compares the output from a delay program counter (18) with the data "end", and sets a flag f end when the comparison result indicates agreement and otherwise resets it.
摘要翻译：本发明涉及一种程序控制单元，其使得程序控制能够实现不立即循环指令并且包含开始地址和结束地址的有效的循环处理。在程序控制单元中，循环处理的起始地址和结束地址分别与时钟t1同步地存储在寄存器（起始）（7）和寄存器（结束）（8）中。寄存器（7）的存储数据“开始”和寄存器（8）的存储数据“结束”分别输入到比较器（12）和比较器（11）。比较器（12）将来自延迟程序计数器（18）的输出与数据“开始”进行比较，并且当比较结果指示一致时设置标志f开始，否则将其复位。比较器（11）将来自延迟程序计数器（18）的输出与数据“结束”进行比较，并且当比较结果表示协议时设定标志f结束，否则将其复位。

99. 发明授权

US5584010A Direct memory access control device and method in a multiprocessor system accessing local and shared memory 失效
标题翻译：直接存储器访问控制设备和方法在多处理器系统中访问本地和共享内存
公开(公告)号：US5584010A
公开(公告)日：1996-12-10
申请号：US358670
申请日：1994-12-19
申请人： Hiroyuki Kawai , Hideyuki Terane
发明人： Hiroyuki Kawai , Hideyuki Terane
IPC分类号： G06F15/16 , G06F13/28 , G06F13/38 , G06F15/163 , G06F13/40 , G06F12/08 , G06F13/36
CPC分类号： G06F13/28
摘要： A direct memory access control device is used in a multiprocessor system having a plurality of digital data processors and an external common memory connected in common to those digital data processors through a first bus. In the case of transferring data in a direct memory access mode between processors, the transfer of data between the processors is effected by the control device through a second data bus provided in common to the plurality of digital data processors separately from the first bus. Thus, data can be transferred directly in a direct memory access mode between the processors without using the external memory and high-speed transfer can be realized. In addition, the control device comprises registers for storing the status bits of each digital data processor, such as direct memory access request and acceptance signals, corresponding to each digital data processor. Request and acceptance of direct memory access and transfer of data are effected by monitoring the contents of those registers.
摘要翻译：直接存储器访问控制装置用于具有多个数字数据处理器和通过第一总线与这些数字数据处理器共同连接的外部公共存储器的多处理器系统。在处理器之间以直接存储器访问模式传送数据的情况下，处理器之间的数据传输由控制设备通过与第一总线分离地与多个数字数据处理器共同提供的第二数据总线来实现。因此，可以在处理器之间的直接存储器访问模式中直接传送数据，而不使用外部存储器，并且可以实现高速传输。此外，控制装置包括用于存储每个数字数据处理器的状态位的寄存器，例如对应于每个数字数据处理器的直接存储器访问请求和接收信号。通过监视这些寄存器的内容来实现对存储器直接访问和数据传输的请求和接受。

100. 发明授权

US5051610A SR latch circuit 失效
标题翻译： SR锁存电路
公开(公告)号：US5051610A
公开(公告)日：1991-09-24
申请号：US456335
申请日：1989-12-26
申请人： Hideyuki Terane , Hiroyuki Kawai
发明人： Hideyuki Terane , Hiroyuki Kawai
IPC分类号： H03K3/356 , H03K3/037
CPC分类号： H03K3/037
摘要： An SR latch is provided, which comprises a D-type latch and a logic circuit connected between data and sense input of the D-type latch and set and reset input terminals of the SR latch circuit. The logic circuit establishes the logic levels of signals applied to the data and sense inputs of the D-type latch such that said SR latch circit can assume one of set, reset and hold states depending on the combination of the logic levels of the signals applied to the set and reset input terminals.
摘要翻译：提供SR锁存器，其包括D型锁存器和连接在D型锁存器的数据和检测输入之间的逻辑电路以及SR锁存器电路的设置和复位输入端子。逻辑电路建立施加到数据的信号的逻辑电平并且感测D型锁存器的输入，使得所述SR锁存器环路可以根据施加的信号的逻辑电平的组合来采取设置，复位和保持状态之一到设置和复位输入端子。

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