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91. 发明申请

US20080012091A1 VERTICAL LC TANK DEVICE 失效
标题翻译：垂直液相色谱箱装置
公开(公告)号：US20080012091A1
公开(公告)日：2008-01-17
申请号：US11859850
申请日：2007-09-24
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L27/02 , H01L27/00 , H01L29/00 , H01L29/93
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译：一种LC粘结结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

92. 发明授权

US07288417B2 On-chip signal transformer for ground noise isolation 有权
标题翻译：用于接地噪声隔离的片上信号变压器
公开(公告)号：US07288417B2
公开(公告)日：2007-10-30
申请号：US10905480
申请日：2005-01-06
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L21/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2019/085 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A mixed-signal chip having a signal transformer located between analog circuitry and digital circuitry. The signal transformer includes a primary winding electrically coupled to the analog circuitry and a secondary winding electrically coupled to the digital circuitry. The primary and secondary windings are magnetically coupled with one another via a magnetic core. The magnetic coupling between the primary and secondary windings inhibits the coupling of electrical noise between the analog and digital circuitries.
摘要翻译：混合信号芯片，具有位于模拟电路和数字电路之间的信号变压器。信号变压器包括电耦合到模拟电路的初级绕组和电耦合到数字电路的次级绕组。初级和次级绕组通过磁芯彼此磁耦合。初级和次级绕组之间的磁耦合阻碍了模拟和数字电路之间的电气噪声耦合。

93. 发明申请

US20070038968A1 INCREASED POWER LINE NOISE IMMUNITY IN IC USING CAPACITOR STRUCTURE IN FILL AREA 失效
标题翻译：使用电容器结构在IC中增加电源线噪声免疫
公开(公告)号：US20070038968A1
公开(公告)日：2007-02-15
申请号：US11161634
申请日：2005-08-10
申请人： Florian Braun , Hanyi Ding , Kai Feng , Zhong-Xiang He , Howard Landis , Xuefeng Liu , Geoffrey Woodhouse
发明人： Florian Braun , Hanyi Ding , Kai Feng , Zhong-Xiang He , Howard Landis , Xuefeng Liu , Geoffrey Woodhouse
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.
摘要翻译：通过在IC的区域中使用去耦电容器结构来提供IC中的电力线噪声抗扰度，该结构通常不用于布线，而是填充有未连接和非功能金属正方形（填充）。在一个实施例中，一种方法包括提供电路设计布局; 确定电路设计布局区域中结构的密度; 并且响应于所述密度小于所述区域中的结构的预定密度，用至少一个电容器结构填充所述区域的一部分，直到所述结构和所述至少一个电容器结构的组合密度在面积约等于预定密度。通过使用通常用非连接和非功能金属形状填充的（填充）区域，通过增加去耦电容而不扩大IC的总尺寸来增加电力线噪声抗扰度。

94. 发明授权

US07071530B1 Multiple layer structure for substrate noise isolation 有权
标题翻译：用于衬底噪声隔离的多层结构
公开(公告)号：US07071530B1
公开(公告)日：2006-07-04
申请号：US10905934
申请日：2005-01-27
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L21/762
CPC分类号： H01L21/76264 , H01L23/552 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.
摘要翻译：一种形成半导体结构的方法，包括：提供具有掩埋绝缘层和重掺杂层的衬底; 在保护区域周围形成衬底内的第一沟槽; 用绝缘材料填充第一沟槽，其中填充有绝缘材料的第一沟槽和埋入绝缘层组合形成高阻抗噪声隔离，围绕保护区域的保护区域，除了保护区域的一侧以隔离噪声保护区; 在所述衬底内围绕所述第一沟槽形成第二沟槽; 以及用导电材料填充所述第二沟槽，其中填充有所述导电材料和所述重掺杂层的所述第二沟槽组合以形成低阻抗接地路径，所述低阻抗接地路径围绕除所述高阻抗噪声的一侧之外的所有侧面上的高阻抗噪声隔离隔离隔离来自保护区的噪音。

95. 发明授权

US07061359B2 On-chip inductor with magnetic core 有权
标题翻译：带磁芯的片上电感
公开(公告)号：US07061359B2
公开(公告)日：2006-06-13
申请号：US10604180
申请日：2003-06-30
申请人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01F5/00
CPC分类号： H01F41/046 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor formed on an integrated circuit chip including one or more inner layers (12) between two or more outer layers (14), inductor metal winding turns (16) included in one or more inner layers (12), and a magnetic material forming the two or more outer layers (14) and the one or more inner layers (12). In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips (32 and 36) disposed on each of the first and second portions (30 and 34, respectively) of the two or more outer layers (14) and on each of the one or more inner layers (12). The series of magnetic metallic strips on the first and second portions (30, 34) form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.
摘要翻译：形成在集成电路芯片上的电感器，其包括在一个或多个内层（12）中包括的两个或多个外层（14），电感器金属绕组匝（16）之间的一个或多个内层（12）两个或多个外层（14）和一个或多个内层（12）。在一个实施例中，磁性材料是具有磁性颗粒的光致抗蚀剂浆料。在另一个实施例中，磁性材料是一系列设置在两个或多个外层（14）的第一和第二部分（30和34）的每一个上的磁性金属条（32和36）一个或多个内层（12）。第一和第二部分（30,34）上的一系列磁性金属条形成网格图案。其他实施例包括具有可调电流的可调控制的化合物沉积和控制绕组。

96. 发明授权

US08860191B2 On-chip transmission line structures with balanced phase delay 有权
标题翻译：具有平衡相位延迟的片上传输线结构
公开(公告)号：US08860191B2
公开(公告)日：2014-10-14
申请号：US13168512
申请日：2011-06-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L23/66 , H01P1/18 , H01L23/522
CPC分类号： H01L23/5222 , H01L23/5225 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01P1/184 , Y10T29/49117 , H01L2924/00
摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.
摘要翻译：一种传输线路结构，相关设计结构及其相关方法。公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为基本上与第二部分相同。

97. 发明授权

US08853693B2 Test structure for determination of TSV depth 有权
标题翻译：用于测定TSV深度的测试结构
公开(公告)号：US08853693B2
公开(公告)日：2014-10-07
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/00 , H01L21/768 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译：半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

98. 发明授权

US08643431B2 On-chip millimeter wave lange coupler 有权
标题翻译：片上毫米波兰光耦合器
公开(公告)号：US08643431B2
公开(公告)日：2014-02-04
申请号：US13277265
申请日：2011-10-20
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H03D3/02 , H01P5/18
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

99. 发明授权

US08566759B2 Structure for on chip shielding structure for integrated circuits or devices on a substrate 有权
标题翻译：用于集成电路或基板上的器件的片上屏蔽结构的结构
公开(公告)号：US08566759B2
公开(公告)日：2013-10-22
申请号：US12046750
申请日：2008-03-12
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： G01R1/18 , G01R31/2851 , H01L23/552 , H01L23/66 , H01L2223/6627 , H01L2223/665 , H01L2924/0002 , H01L2924/1903 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置分别。该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

100. 发明授权

US08518787B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08518787B2
公开(公告)日：2013-08-27
申请号：US13604731
申请日：2012-09-06
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L21/763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

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