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91. 发明授权

US08065491B2 Efficient non-transactional write barriers for strong atomicity 有权
标题翻译：有效的非事务性写入障碍，用于强原子性
公开(公告)号：US08065491B2
公开(公告)日：2011-11-22
申请号：US11967232
申请日：2007-12-30
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译：这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。在初始非事务写入到存储器位置时获取锁定。维护锁，直到检测到事件导致锁的释放。结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对被锁定的存储器位置的任何后续写入。

92. 发明申请

US20110276761A1 ACCELERATING SOFTWARE LOOKUPS BY USING BUFFERED OR EPHEMERAL STORES 有权
标题翻译：通过使用缓冲存储或加速存储来加速软件查询
公开(公告)号：US20110276761A1
公开(公告)日：2011-11-10
申请号：US13104681
申请日：2011-05-10
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Etban Schuchman
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Etban Schuchman
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F2212/507
摘要： A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible.
摘要翻译：这里描述用于加速基于地址的表中的查找的方法和装置。当地址和值对被添加到基于地址的表中时，该值被私人地存储在地址中，以便能够快速高效地本地访问该值。响应于私有存储，保存该值的高速缓存行被转换到私有状态，以确保该值不是全局可见的。撤销私有高速缓存行时，信息不会被写回以确保价值的位置。在一个实施例中，基于地址的表包括用于保存地址的事务写入缓冲器，其对应于事务期间的暂时更新的值。可以通过使用如本文所讨论的注释位和专用存储来加速在事务期间访问临时值。在提交事务时，将将值复制到位置，以使更新全局可见。

93. 发明申请

US20110271017A1 EFFICIENT NON-TRANSACTIONAL WRITE BARRIERS FOR STRONG ATOMICITY 有权
标题翻译：有效的非事务性写作障碍强大的原子性
公开(公告)号：US20110271017A1
公开(公告)日：2011-11-03
申请号：US13182162
申请日：2011-07-13
申请人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
发明人： Tatiana Shpeisman , Ali-Reza Adl-Tabatabai , Vijay Menon , Bratin Saha
IPC分类号： G06F5/14
CPC分类号： G06F12/0804 , G06F9/3834 , G06F9/3863 , G06F9/466 , G06F9/52 , G06F9/522 , G06F12/0897 , G06F12/1027
摘要： A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
摘要翻译：这里描述了用于为非事务写入提供优化的强原子性操作的方法和装置。在初始非事务写入到存储器位置时获取锁定。维护锁，直到检测到事件导致锁的释放。结果，在获取和释放锁之间的中间期，通过不执行锁获取操作来加速对锁定的存储器位置的任何后续写入。

94. 发明申请

US20110197029A1 HARDWARE ACCELERATION OF A WRITE-BUFFERING SOFTWARE TRANSACTIONAL MEMORY 有权
标题翻译：写硬缓存软件的硬件加速
公开(公告)号：US20110197029A1
公开(公告)日：2011-08-11
申请号：US13094370
申请日：2011-04-26
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F9/467 , G06F12/0842
摘要： A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.
摘要翻译：本文描述了用于加速软件事务存储器（STM）系统的方法和装置。注释字段与事务存储器的行相关联。与事务存储器的行相关联的注释字段在启动事务时被初始化为第一个值。响应于在事务中遇到读取操作，则检查注释字段。如果注释字段包含第一个值，则读取将从事务存储器的行提供服务，而不必搜索额外的写入空间。注释字段中的第二和第三个值潜在地指示读操作是否错过事务存储器或暂存值是否存储在写空间中。此外，注释字段中的另外一个位可以用于指示是否已经记录先前的读取操作，从而允许减少随后的冗余读取记录。

95. 发明授权

US07870545B2 Protecting shared variables in a software transactional memory system 有权
标题翻译：保护软件事务内存系统中的共享变量
公开(公告)号：US07870545B2
公开(公告)日：2011-01-11
申请号：US11305634
申请日：2005-12-16
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/45 , G06F9/46
CPC分类号： G06F9/467
摘要： For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an access to the variable that occurs outside any STM-defined critical region system by starting a hardware based transactional memory based transaction, within the hardware based transactional memory based transaction, checking if the variable is currently owned by a STM transaction, checking if the variable is currently owned by a STM transaction; if the variable is not currently owned by a STM transaction, performing the access and then committing the hardware based transactional memory transaction; and if the variable is currently owned by a STM transaction, performing a responsive action.
摘要翻译：对于在程序的基于软件的事务存储系统（STM）定义（STM）定义的关键区域中至少访问一次的变量，通过启动硬件来修改对任何STM定义的关键区域系统之外发生的变量的访问在基于硬件的基于事务内存的事务中，检查变量当前是否由STM事务拥有，检查变量当前是否由STM事务拥有; 如果该变量当前不属于STM事务，则执行该访问，然后提交基于硬件的事务内存事务; 并且如果变量当前由STM事务所拥有，则执行响应动作。

96. 发明申请

US20100332808A1 MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：在不必要的交易记忆系统中最小化代码重复
公开(公告)号：US20100332808A1
公开(公告)日：2010-12-30
申请号：US12493168
申请日：2009-06-26
申请人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3004 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3857 , G06F9/467
摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
摘要翻译：最大限度地减少无界事务内存系统中的代码重复。一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作与未来的TM实现可能会引入未知的未来TM执行模式。

97. 发明授权

US07725662B2 Hardware acceleration for a software transactional memory system 有权
标题翻译：软件交易内存系统的硬件加速
公开(公告)号：US07725662B2
公开(公告)日：2010-05-25
申请号：US11926440
申请日：2007-10-29
申请人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn A. Jacobson
发明人： Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn A. Jacobson
IPC分类号： G06F13/376
CPC分类号： G06F13/4243 , G06F9/3834 , G06F9/466 , G06F9/526
摘要： A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
摘要翻译：一种用于加速事务执行的方法和装置。只有在事务中第一次访问共享内存条时，才会调用/执行与事务中的内存访问引用的共享内存条相关联的障碍。提供诸如事务字段/事务位之类的硬件支持来确定访问是否是在事务挂起期间对共享存储器行的第一次访问。另外，在积极的操作模式中，代表存储在共享存储器行中的元素的版本号的版本号在保存验证成本的承诺时不被存储和验证。而且，即使在谨慎的模式下，存储版本号以启用验证，如果在执行交易期间没有发生访问的共享内存条的驱逐，则可能不会产生验证成本。

98. 发明申请

US20100122073A1 HANDLING EXCEPTIONS IN SOFTWARE TRANSACTIONAL MEMORY SYSTEMS 审中-公开
标题翻译：软件交易式存储系统中的处理例外
公开(公告)号：US20100122073A1
公开(公告)日：2010-05-13
申请号：US12268276
申请日：2008-11-10
申请人： Ravi Narayanaswamy , Xinmin Tian , Bratin Saha , Ali-Reza Adl-Tabatabai , Robert Geva , Clark Nelson , Sergey Preis , Sergey Kozhukhov , Aleksei G. Cherkasov
发明人： Ravi Narayanaswamy , Xinmin Tian , Bratin Saha , Ali-Reza Adl-Tabatabai , Robert Geva , Clark Nelson , Sergey Preis , Sergey Kozhukhov , Aleksei G. Cherkasov
IPC分类号： G06F9/30
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/3861 , G06F9/467 , G06F9/4812 , G06F2209/481
摘要： A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit.
摘要翻译：这里描述用于在执行交易期间处理异常的方法和装置。编译器将事务异常处理程序（TEH）与程序代码中的事务相关联，例如通过插入到TEH的调用。 TEH还与异常数据结构相关联，例如展开表，其在运行时期间用于响应于异常来调用适当的处理程序。此外，TEH代码由编译器生成并插入到程序代码中。在执行事务期间遇到异常时，TEH能够通过尝试提交来将事务动态地调整到异常点。

99. 发明申请

US20100057740A1 ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY 审中-公开
公开(公告)号：US20100057740A1
公开(公告)日：2010-03-04
申请号：US12198852
申请日：2008-08-26
申请人： Yang Ni , Richard Myungon Yoo , Adam Wojciech Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Yang Ni , Richard Myungon Yoo , Adam Wojciech Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/46 , G06F17/30 , G06F7/00
CPC分类号： G06F9/466
摘要： A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.

100. 发明申请

US20080162881A1 Mechanism for irrevocable transactions 有权
标题翻译：不可撤销交易的机制
公开(公告)号：US20080162881A1
公开(公告)日：2008-07-03
申请号：US11648485
申请日：2006-12-28
申请人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/40
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/3863
摘要： A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.
摘要翻译：这里描述用于指定和处理不可撤销交易的方法和装置。响应于检测到诸如I / O操作，用户定义的不可撤销指定和动态故障简档的不可撤销事件，交易被指定为不可撤销。为了将交易指定为不可撤销，单独所有者读取锁（SORL）是为不可撤销地指定的事务中的先前和后续读取而获取的，以确保事务能够完成，而无需修改读取的位置，同时允许远程资源从那些位置继续执行。

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