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91. 发明授权

US08030736B2 Fin anti-fuse with reduced programming voltage 有权
标题翻译： Fin反熔丝具有降低的编程电压
公开(公告)号：US08030736B2
公开(公告)日：2011-10-04
申请号：US12538381
申请日：2009-08-10
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins.
摘要翻译：一种形成抗熔丝结构的方法包括位于基板上的多个平行的导电翅片，每个翼片具有第一端和第二端。第二电导体电连接到散热片的第二端。绝缘体覆盖翅片的第一端并且第一电导体位于绝缘体上。第一电导体通过绝缘体与散热片的第一端电绝缘。绝缘体形成为足以在第二电导体和第一电导体之间施加预定电压时分解的厚度，从而通过翅片在第二电导体和第一电导体之间形成不间断的电连接。

92. 发明申请

US20110227165A1 HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
公开(公告)号：US20110227165A1
公开(公告)日：2011-09-22
申请号：US13151525
申请日：2011-06-02
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

93. 发明授权

US08022488B2 High-performance FETs with embedded stressors 有权
标题翻译：具有嵌入式应力的高性能FET
公开(公告)号：US08022488B2
公开(公告)日：2011-09-20
申请号：US12566004
申请日：2009-09-24
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/2257 , H01L21/26586 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
摘要翻译：提供了高性能半导体结构和制造这种结构的方法。半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

94. 发明授权

US08008696B2 Band gap modulated optical sensor 有权
标题翻译：带隙调制光传感器
公开(公告)号：US08008696B2
公开(公告)日：2011-08-30
申请号：US12146575
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L29/72
CPC分类号： H01L27/14645 , H01L27/14627
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。此外，还提供了本发明的互补金属氧化物半导体（CMOS）图像传感器的设计结构。

95. 发明授权

US08003488B2 Shallow trench isolation structure compatible with SOI embedded DRAM 有权
标题翻译：浅沟槽隔离结构与SOI嵌入式DRAM兼容
公开(公告)号：US08003488B2
公开(公告)日：2011-08-23
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

96. 发明授权

US08003455B2 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US08003455B2
公开(公告)日：2011-08-23
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在基板上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

97. 发明授权

US07993999B2 High-K/metal gate CMOS finFET with improved pFET threshold voltage 有权
标题翻译：高K /金属栅极CMOS finFET，具有改善的pFET阈值电压
公开(公告)号：US07993999B2
公开(公告)日：2011-08-09
申请号：US12614906
申请日：2009-11-09
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.
摘要翻译：用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。施主材料外延地沉积在鳍结构的暴露的侧壁上。施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。施主材料被去除，并且从翅片结构形成场效应晶体管。

98. 发明申请

US20110169065A1 METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES 有权
标题翻译：在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构
公开(公告)号：US20110169065A1
公开(公告)日：2011-07-14
申请号：US12686403
申请日：2010-01-13
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/06 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译：提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。还提供了一种用于形成上述装置的方法。

99. 发明授权

US07951657B2 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
标题翻译：在绝缘体上硅（S0I）晶片上形成具有嵌入式和多面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构
公开(公告)号：US07951657B2
公开(公告)日：2011-05-31
申请号：US12470001
申请日：2009-05-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L21/84
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以便选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

100. 发明申请

US20110115023A1 HYBRID FinFET/PLANAR SOI FETs 有权
标题翻译：混合FinFET /平面SOI FET
公开(公告)号：US20110115023A1
公开(公告)日：2011-05-19
申请号：US12621460
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823878 , H01L27/1211 , H01L29/785
摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.
摘要翻译：公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。三种不同类型的设备中的每一种具有单独优化的阈值。还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

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