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91. 发明授权

US08635180B2 Multiple hash scheme for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的多个哈希方案
公开(公告)号：US08635180B2
公开(公告)日：2014-01-21
申请号：US13021757
申请日：2011-02-06
申请人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy Hume Heil , Jan Van Lunteren
IPC分类号： G06N5/04
CPC分类号： G06N5/047 , G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。定义模式上下文集的正则表达式集合被编译为生成由PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

92. 发明申请

US20130321180A1 METHOD OF ACCELERATING DYNAMIC HUFFMAN DECOMPACTION WITHIN THE INFLATE ALGORITHM 有权
标题翻译：在加速算法中加速动态失效分解的方法
公开(公告)号：US20130321180A1
公开(公告)日：2013-12-05
申请号：US13484296
申请日：2012-05-31
申请人： Giora Biran , Amit Golander , Shai Ishaya Tahar
发明人： Giora Biran , Amit Golander , Shai Ishaya Tahar
IPC分类号： H03M7/40
CPC分类号： H03M7/425 , H03M7/40 , H03M7/405
摘要： A system and method of accelerating dynamic Huffman decompaction within the inflate algorithm. To improve the performance of a decompression engine during the inflate/decompression process, Huffman trees decompacted a priori are used thus eliminating the requirement of decompacting the DHT for each input stream. The Huffman tree in the input stream is matched prior to decompaction. If a match is found, the stored decompacted Huffman tree is used which reduces the required decompression time.
摘要翻译：在充气算法中加速动态霍夫曼分解的系统和方法。为了在充气/解压缩过程中提高解压缩引擎的性能，使用先验解压缩的霍夫曼树，从而消除了对每个输入流解码DHT的要求。输入流中的霍夫曼树在分解前进行匹配。如果找到匹配，则使用存储的分解的霍夫曼树，这降低了所需的减压时间。

93. 发明授权

US08402003B2 Performance monitoring mechanism for use in a pattern matching accelerator 失效
标题翻译：用于模式匹配加速器的性能监视机制
公开(公告)号：US08402003B2
公开(公告)日：2013-03-19
申请号：US13022904
申请日：2011-02-08
申请人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
发明人： Giora Biran , Christoph Hagleitner , Timothy H. Heil , Jan Van Lunteren
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译：模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。在输入流中要搜索的模式由用户定义为一组正则表达式。要搜索的模式分组在模式上下文集中。编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。对于每个输入字符，PMA执行搜索并返回搜索结果。

94. 发明申请

US20120254587A1 ACCELERATOR ENGINE COMMANDS SUBMISSION OVER AN INTERCONNECT LINK 有权
标题翻译：加速器发动机命令通过互连链路提交
公开(公告)号：US20120254587A1
公开(公告)日：2012-10-04
申请号：US13077804
申请日：2011-03-31
申请人： Giora Biran , Ilya Granovsky
发明人： Giora Biran , Ilya Granovsky
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3877 , G06F9/547 , G06F13/38 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F2213/0026
摘要： An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command.
摘要翻译：通过诸如PCI Express（PCIe）链路的互连链路提交硬件加速器引擎命令的装置和方法。在一个实施例中，该机制在集成到主机IC或芯片组中的PCIe主机桥内部实现。该机制提供了与其他集成加速器兼容的接口，从而消除了为本地和远程加速器维护不同编程模型的开销。请求针对远程加速器的服务（客户端线程）的线程发出的协处理器请求排队，并通过PCIe链路发送到PCIe适配器和远程加速器引擎。远程加速器引擎执行所请求的处理任务，将结果传回主机存储器，并且PCIe主机桥执行协处理器请求完成序列（状态更新，写入标志，中断）包括在协处理器命令中。

95. 发明申请

US20100253556A1 METHOD OF CONSTRUCTING AN APPROXIMATED DYNAMIC HUFFMAN TABLE FOR USE IN DATA COMPRESSION 有权
标题翻译：构建用于数据压缩的大致动态霍夫曼表的方法
公开(公告)号：US20100253556A1
公开(公告)日：2010-10-07
申请号：US12418896
申请日：2009-04-06
申请人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
发明人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
IPC分类号： H03M7/40
CPC分类号： H03M7/40
摘要： A novel and useful method of constructing a fast approximation of a dynamic Huffman table from a data sample comprising a subset of data to be compressed. The frequency of incidence of each symbol in the sample is calculated, and the symbols are then allocated to predefined bins based on their frequency of incidence. The bins are then transformed into binary sub-trees, where the leaf nodes of the binary sub-trees comprise the symbols of the bin associated with the binary sub-trees. The binary sub-trees are then combined via nesting, thereby creating a coarse grained binary tree, where all leaves are mapped to a specified number of depths. The coarse grained binary tree is then traversed, thereby yielding a canonical code for each symbol, thereby defining the entries for a dynamic Huffman table.
摘要翻译：一种从包括要压缩的数据的子集的数据样本构建动态霍夫曼表的快速近似的新颖且有用的方法。计算样本中每个符号的入射频率，然后根据其入射频率将符号分配给预定义的分组。然后，将这些分组转换成二进制子树，其中二进制子树的叶节点包括与二进制子树相关联的bin的符号。然后通过嵌套组合二进制子树，从而创建粗粒度二叉树，其中所有叶被映射到指定数量的深度。然后遍历粗粒二进制树，从而为每个符号产生规范代码，从而为动态霍夫曼表定义条目。

96. 发明授权

US07692561B2 Method and apparatus for data decompression in the presence of memory hierarchies 有权
标题翻译：在存在层次结构的情况下进行数据解压缩的方法和装置
公开(公告)号：US07692561B2
公开(公告)日：2010-04-06
申请号：US12175214
申请日：2008-07-17
申请人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
发明人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
IPC分类号： H03M7/34
CPC分类号： H03M7/3086
摘要： A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that the first data is located in the remote memory, stalling the first decompression copy operation, performing a second decompression operation using second data that is located in the history buffer on the local memory and fetching the first data from the remote memory to the history buffer on the local memory. The method further includes performing the first decompression operation using the first data in the history buffer on the local memory.
摘要翻译：用于对压缩数据分组的流进行解压缩的方法包括：确定用于第一解压缩复制操作的数据字典的第一数据是否位于远程存储器或本地存储器上的历史缓冲器中，以及当确定第一数据位于远程存储器中，停止第一次解压缩复制操作，使用位于本地存储器上的历史缓冲器中的第二数据执行第二次解压缩操作，并将第一数据从远程存储器读取到本地的历史缓冲区记忆。该方法还包括使用本地存储器上的历史缓冲器中的第一数据来执行第一解压缩操作。

97. 发明申请

US20100013678A1 METHOD AND APPARATUS FOR DATA DECOMPRESSION IN THE PRESENCE OF MEMORY HIERARCHIES 有权
标题翻译：存储分层存在的数据分解方法与装置
公开(公告)号：US20100013678A1
公开(公告)日：2010-01-21
申请号：US12175214
申请日：2008-07-17
申请人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
发明人： Giora Biran , Hubertus Franke , Amit Golander , Hao Yu
IPC分类号： H03M5/00
CPC分类号： H03M7/3086
摘要： A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that the first data is located in the remote memory, stalling the first decompression copy operation, performing a second decompression operation using second data that is located in the history buffer on the local memory and fetching the first data from the remote memory to the history buffer on the local memory. The method further includes performing the first decompression operation using the first data in the history buffer on the local memory.
摘要翻译：用于对压缩数据分组的流进行解压缩的方法包括：确定用于第一解压缩复制操作的数据字典的第一数据是否位于远程存储器或本地存储器上的历史缓冲器中，以及当确定第一数据位于远程存储器中，停止第一次解压缩复制操作，使用位于本地存储器上的历史缓冲器中的第二数据执行第二次解压缩操作，并将第一数据从远程存储器读取到本地的历史缓冲区记忆。该方法还包括使用本地存储器上的历史缓冲器中的第一数据来执行第一解压缩操作。

98. 发明申请

US20090006932A1 Device, System and Method of Modification of PCI Express Packet Digest 有权
标题翻译： PCI Express数据包摘要的设备，系统和方法
公开(公告)号：US20090006932A1
公开(公告)日：2009-01-01
申请号：US11771238
申请日：2007-06-29
申请人： Giora Biran , Ilya Granovsky , Elchanan Perlin
发明人： Giora Biran , Ilya Granovsky , Elchanan Perlin
IPC分类号： G06F11/10
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.
摘要翻译： PCI Express数据包摘要的设备，系统和修改方法。例如，设备包括基于信用的流控制互连设备，用于生成基于信用的流控制互连事务层分组，其中摘要部分的一个或多个位携带非ECRC数据。

99. 发明申请

US20080168259A1 Descriptor Prefetch Mechanism for High Latency and Out of Order DMA Device 有权
标题翻译：高延迟和超出DMA设备的描述符预取机制
公开(公告)号：US20080168259A1
公开(公告)日：2008-07-10
申请号：US11621789
申请日：2007-01-10
申请人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
发明人： Giora Biran , Luis E. De la Torre , Bernard C. Drerup , Jyoti Gupta , Richard Nicholas
IPC分类号： G06F9/30 , G06F12/14 , G06F11/00
CPC分类号： G06F13/28
摘要： A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.
摘要翻译： DMA设备将描述符预取到描述符预取缓冲区中。描述符预取缓冲区的大小在给定的等待时间环境中保存适当数量的描述符。为了支持描述符的链表，DMA引擎基于它们在存储器中是连续的假设来预取描述符，并丢弃任何被发现违反这个假设的描述符。 DMA引擎寻求通过每个事务请求多个描述符尽可能地保持描述符预取缓冲区已满。总线引擎从系统内存中读取这些描述符，并将它们写入预取缓冲区。 DMA引擎还可以使用积极的预取，其中总线引擎请求缓冲区将在描述符预取缓冲器中存在任何空间时将支持的最大数量的描述符。 DMA设备丢弃任何其他不能存储的描述符。

100. 发明申请

US20060190659A1 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US20060190659A1
公开(公告)日：2006-08-24
申请号：US11064568
申请日：2005-02-24
申请人： Giora Biran , Robert Drehmel , Robert Horton , Mark Kautzman , Jamie Kuesel , Ming-i Lin , Eric Mejdrich , Clarence Ogilvie , Charles Woodruff
发明人： Giora Biran , Robert Drehmel , Robert Horton , Mark Kautzman , Jamie Kuesel , Ming-i Lin , Eric Mejdrich , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
摘要翻译：高速计算机总线与高速输出总线之间的总线桥。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI）之间的总线桥。另一个优选实施例是多芯片模块上的总线收发器中的总线桥。

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