专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06621817B1 Transport packet parser 有权
标题翻译：传输数据包解析器
公开(公告)号：US06621817B1
公开(公告)日：2003-09-16
申请号：US09348103
申请日：1999-07-06
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： H04L1228
CPC分类号： H04L49/3009 , H04L49/20
摘要： A transport packet parser (42) includes a transport packet header decoder (50)for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packets satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.
摘要翻译：传输分组解析器（42）包括用于识别与当前分组相关联的分组标识符（PID）和连续性计数器（CC）的传输分组报头解码器（50）。在搜索模式下，将PID与使能（En）位一起输入到PID关联存储器（52），以识别与PID相关联的地址。地址用于在随机存取存储器（62）中访问与先前分组相关联的用于相同PID的CC。先前的连续性计数器与其他报头信息一起使用以确定当前分组是否满足预定标准。如果是这样，则将分组传递到传输分组缓冲器以进一步处理。

92. 发明授权

US06414726B1 Device for identifying packets of digital data and a receiver for digital television signals equipped with such a device 失效
标题翻译：用于识别数字数据包的装置和配备有这种装置的数字电视信号的接收机
公开(公告)号：US06414726B1
公开(公告)日：2002-07-02
申请号：US08961958
申请日：1997-10-31
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： H04N5455
CPC分类号： H04N21/42653 , G09G5/14 , G09G5/395 , H04L29/06 , H04L69/22 , H04N5/4401 , H04N5/44508 , H04N19/42 , H04N19/61 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/431 , H04N21/434 , H04N21/439 , H04N21/44 , H04N21/443
摘要： Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.
摘要翻译：提供了用于识别数字数据分组的电路，每个包括有用信号和包含与有用信号的内容有关的数据的报头信号。该电路包括用于从每个标题信号中提取数据的装置（30），该数据表示对应的有用信号，用于将参考数据存储在存储器中的每个对应于分组类型的地址的装置和用于比较的装置从具有存储在存储器中的所述参考数据的每个报头信号中提取的数据以及用于传送指示相应分组的性质的地址信号的数据处理单元（32,34）。数据存储装置和比较装置优选地采用适于确保从每个报头信号提取的数据与存储在存储器中的参考数据同时进行比较的关联存储器（38）。

93. 发明授权

US6000026A Multiple processor apparatus having a protocol processor intended for the execution of a collection of instructions in a reduced number of operations 失效
标题翻译：具有协议处理器的多处理器装置旨在用于执行减少数量的操作的指令集合
公开(公告)号：US6000026A
公开(公告)日：1999-12-07
申请号：US990151
申请日：1997-12-12
申请人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
发明人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
IPC分类号： G06F9/308 , G06F9/38 , G06F15/16
CPC分类号： G06F9/3879 , G06F9/30018 , G06F9/3877
摘要： Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.
摘要翻译：旨在与系统的至少一个主处理器相关联的协议处理器，以便执行主处理器不适合的任务。协议处理器包括一个包括递增寄存器（31）的程序部分（30），连接到增量寄存器（31）以便接收地址的程序存储器（33），用于接收来自程序部分（30）的程序存储器（33），用于执行两个周期的指令，以及用于执行指令的数据部分（36）。

94. 发明授权

US5867408A Process and device with digital signal processor for the implementation of a viterbi algorithm 失效
标题翻译：具有数字信号处理器的过程和设备，用于实施维特比算法
公开(公告)号：US5867408A
公开(公告)日：1999-02-02
申请号：US942735
申请日：1997-10-02
申请人： Gerard Chauvel , Jean-Luc Villevieille
发明人： Gerard Chauvel , Jean-Luc Villevieille
IPC分类号： H03H17/02 , G06F7/00 , G06F11/10 , G06F17/10 , H03M13/23 , H03M13/41
CPC分类号： H03M13/6502 , H03M13/41
摘要： This devise comprising a digital signal processor (1) proper, a ROM program memory (2) and a RAM data memory (3) which are connected respectively to the processor, is characterized in that associated with the RAM data memory is a RAM viterbi memory (7) including means for executing addition, comparison and selection operations of the Viterbi algorithm, and logic (8) for controlling the Viterbi memory (7).
摘要翻译：其特征在于，包括分别连接到处理器的数字信号处理器（1），ROM程序存储器（2）和RAM数据存储器（3），其特征在于与RAM数据存储器相关联的是RAM维特比存储器（7）包括用于执行维特比算法的相加，比较和选择操作的装置以及用于控制维特比存储器（7）的逻辑（8）。

95. 发明授权

US5740458A Protocol processor intended for the execution of a collection of instructions in a reduced number of operations 失效
标题翻译：协议处理器旨在用于执行减少数量的操作的指令集合
公开(公告)号：US5740458A
公开(公告)日：1998-04-14
申请号：US902191
申请日：1992-06-22
申请人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
发明人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
IPC分类号： G06F9/308 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3879 , G06F9/30018 , G06F9/3877
摘要： Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.
摘要翻译：旨在与系统的至少一个主处理器相关联的协议处理器，以便执行主处理器不适合的任务。协议处理器包括一个包括递增寄存器（31）的程序部分（30），连接到增量寄存器（31）以便接收地址的程序存储器（33），用于接收来自程序部分（30）的程序存储器（33），用于执行两个周期的指令，以及用于执行指令的数据部分（36）。

96. 发明授权

US4827249A Video system with combined text and graphics frame memory 失效
标题翻译：具有组合文字和图形帧存储器的视频系统
公开(公告)号：US4827249A
公开(公告)日：1989-05-02
申请号：US082965
申请日：1987-08-05
申请人： Gerard Chauvel , Frederic Boutaud
发明人： Gerard Chauvel , Frederic Boutaud
IPC分类号： G09G1/02 , G09G1/06 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/30 , G09G5/36 , G09G5/39 , G09G5/42
CPC分类号： G09G5/022 , G09G5/42
摘要： This system includes a composite memory (5) in which are memorized the data for images to be displayed for each frame. A video display processor (12) controls the screen (8). A central processing unit (1) effects the composition of the image with the memory and an address processor (10), the extraction of the point data to be displayed being effected by a time base circuit (BT) synchronized with the sweeping of the screen, and by a control device (15) for dynamic access which distributes the access times among different units utilizing the memory. The memory (5) includes a first control memory for the memorization of a data word for a line or group of lines making up the image, each word having an address value for addressing a second control memory which contains, at each of these addresses, at least one display attribute data word characterizing the contents of the line(s) corresponding to the value of the respective address of the first control memory. A zone memory is provided for storing, in addressable zones, the text or graphics information for those lines which have intelligible information. For each of the lines having such information, a data word following the display attribute data word contains the initial address in the zone memory of the corresponding zone which contains the intelligible information to be displayed on the line.
摘要翻译：该系统包括复合存储器（5），其中存储要针对每帧显示的图像的数据。视频显示处理器（12）控制屏幕（8）。中央处理单元（1）利用存储器和地址处理器（10）实现图像的组成，通过与屏幕扫描同步的时基电路（BT）来实现要显示的点数据的提取，以及用于利用存储器在不同单元之间分配访问时间的用于动态访问的控制设备（15）。存储器（5）包括用于存储构成图像的一行或一组线的数据字的第一控制存储器，每个字具有用于寻址第二控制存储器的地址值，该第二控制存储器在每个这些地址处包含至少一个显示属性数据字表征对应于第一控制存储器的相应地址的值的行的内容。提供区域存储器用于在可寻址区域中存储具有可理解信息的那些线路的文本或图形信息。对于具有这种信息的每一行，显示属性数据字之后的数据字包含相应区域的区域存储器中的初始地址，其中包含要在该行上显示的可理解信息。

97. 发明授权

US4562812A Electronic ignition control for internal combustion engine 失效
标题翻译：内燃机电子点火控制
公开(公告)号：US4562812A
公开(公告)日：1986-01-07
申请号：US572500
申请日：1984-01-20
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： F02P5/15 , F02P7/077 , F02P5/00
CPC分类号： F02P5/1502 , F02P7/0775 , Y02T10/46
摘要： Method and apparatus for ignition control of an internal combustion engine provide for computation of an ignition instant based upon operating parameters of the engine measured during a preceding ignition cycle. A device for controlling the ignition of the engine includes a central calculating unit (17) and a peripheral input/output unit (1) controlled by a micro-code program stored in a micro-code ROM (18). Computation of engine speed is accomplished by a disk (5a) having teeth on the periphery (5b), and cooperating with a magnetic detector (5d), the disk being rigid with the crankshaft of the engine to be controlled.
摘要翻译：用于内燃机点火控制的方法和装置提供基于在先前点火循环期间测量的发动机的操作参数的点火时刻的计算。用于控制发动机点火的装置包括由存储在微码ROM（18）中的微码程序控制的中央计算单元（17）和外围输入/输出单元（1）。发动机速度的计算由在周边（5b）上具有齿的盘（5a）实现，并且与磁检测器（5d）配合，该盘与待控制的发动机曲轴是刚性的。

98. 发明授权

US08516496B2 Storing contexts for thread switching 有权
标题翻译：存储线程切换的上下文
公开(公告)号：US08516496B2
公开(公告)日：2013-08-20
申请号：US11186315
申请日：2005-07-21
申请人： Gilbert Cabillic , Gerard Chauvel
发明人： Gilbert Cabillic , Gerard Chauvel
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.
摘要翻译：一种电子设备，包括解码逻辑，其解码指令和耦合到解码逻辑的堆栈。一组指令使解码逻辑推到堆栈上，在停止处理切换点处的第一线程并且在处理第二线程之前，在切换点恢复执行第一线程所需的最少量的信息而不是在切换点恢复执行第一个线程所需的信息。

99. 发明授权

US07757223B2 Method and system to construct a data-flow analyzer for a bytecode verifier 有权
标题翻译：构建字节码验证器的数据流分析器的方法和系统
公开(公告)号：US07757223B2
公开(公告)日：2010-07-13
申请号：US11188502
申请日：2005-07-25
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Mikael Peltier , Gerard Chauvel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
摘要翻译：上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。

100. 发明授权

US07624382B2 Method and system of control flow graph construction 有权
标题翻译：控制流程图构建方法与系统
公开(公告)号：US07624382B2
公开(公告)日：2009-11-24
申请号：US11189367
申请日：2005-07-26
申请人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic , Mikael Peltier
发明人： Gerard Chauvel , Jean-Philippe Lesot , Gilbert Cabillic , Mikael Peltier
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.
摘要翻译：一种通过使用硬件执行微序列构建控制流程图的方法和系统。一些说明性实施例是包括从存储器检索指令的获取逻辑的处理器，作为程序的一部分的指令以及耦合到解码指令的取指逻辑的解码逻辑，其中由解码逻辑解码的指令触发执行微序列在控制流程图中输入指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式