专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07838392B2 Methods for forming III-V semiconductor device structures 有权
标题翻译：形成III-V半导体器件结构的方法
公开(公告)号：US07838392B2
公开(公告)日：2010-11-23
申请号：US11943188
申请日：2007-11-20
申请人： Thomas A. Langdo , Matthew T. Currie , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
发明人： Thomas A. Langdo , Matthew T. Currie , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
IPC分类号： H01L21/30
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

92. 发明授权

US07588994B2 Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain 有权
标题翻译：通过机械诱导应变形成绝缘体上半导体器件结构的方法
公开(公告)号：US07588994B2
公开(公告)日：2009-09-15
申请号：US11128628
申请日：2005-05-13
申请人： Thomas A. Langdo , Matthew T. Currie , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
发明人： Thomas A. Langdo , Matthew T. Currie , Richard Hammond , Anthony J. Lochtefeld , Eugene A. Fitzgerald
IPC分类号： H01L21/46
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

93. 发明申请

US20090114902A1 TENSILE STRAINED GE FOR ELECTRONIC AND OPTOELECTRONIC APPLICATIONS 有权
标题翻译：电子和光电应用的拉伸应变通道
公开(公告)号：US20090114902A1
公开(公告)日：2009-05-07
申请号：US12265976
申请日：2008-11-06
申请人： Yu Bai , Minjoo L. Lee , Eugene A. Fitzgerald
发明人： Yu Bai , Minjoo L. Lee , Eugene A. Fitzgerald
IPC分类号： H01L29/15 , H01L21/20
CPC分类号： H01L21/0251 , B82Y10/00 , H01L21/02395 , H01L21/0245 , H01L21/02452 , H01L21/02463 , H01L21/02532 , H01L21/02535 , H01L29/1054 , Y10S438/933 , Y10S438/938
摘要： A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.
摘要翻译：提供半导体结构。半导体结构包括一个或多个III-IV材料基半导体层。在一个或多个III-IV材料基半导体层上形成拉伸应变Ge层。拉伸应变Ge层通过在一个或多个III-IV材料基半导体层上的晶格失配的异质外延产生。

94. 发明授权

US07501351B2 Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits 有权
标题翻译：轻松的SiGe平台，用于高速CMOS电子和高速模拟电路
公开(公告)号：US07501351B2
公开(公告)日：2009-03-10
申请号：US10774890
申请日：2004-02-09
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/31
CPC分类号： H01L29/802 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/76251 , H01L21/76256 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/1054 , H01L29/66893 , H01L29/66916 , H01L29/7838
摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
摘要翻译：使用平面弛豫SiGe作为材料平台制造高速数字，模拟和组合数字/模拟系统的结构和方法。松弛的SiGe允许具有增强的电子特性的大量应变Si层。通过允许MOSFET通道处于表面或掩埋，可以创建高速数字和/或模拟电路。在沉积器件外延层之前的平坦化确保了用于最先进光刻的平坦表面。

95. 发明授权

US07495266B2 Strained silicon-on-silicon by wafer bonding and layer transfer 有权
标题翻译：通过晶片接合和层转移来应变硅上硅
公开(公告)号：US07495266B2
公开(公告)日：2009-02-24
申请号：US10869814
申请日：2004-06-16
申请人： David M. Isaacson , Eugene A. Fitzgerald
发明人： David M. Isaacson , Eugene A. Fitzgerald
IPC分类号： H01L31/0328
CPC分类号： H01L21/187
摘要： A semiconductor-based structure includes first and second layers bonded directly to each other at an interface. Parallel to the interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer. The first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes providing first and second layers that are formed of essentially the same semiconductor. The first and second layers have, respectively, first and second surfaces. The second layer has a different lattice spacing parallel to the second surface than the lattice spacing of the first layer parallel to the first surface. The method includes contacting the first and second surfaces, and annealing to promote direct atomic bonding between the first and second layers.
摘要翻译：基于半导体的结构包括在界面处彼此直接键合的第一和第二层。平行于界面，第二层的晶格间距不同于第一层的晶格间距。第一层和第二层各自由基本上相同的半导体形成。制造基于半导体的结构的方法包括提供由基本上相同的半导体形成的第一和第二层。第一和第二层分别具有第一和第二表面。第二层具有与第一层平行于第一表面的晶格间隔平行于第二表面的不同晶格间距。该方法包括使第一和第二表面接触，退火以促进第一和第二层之间的直接原子结合。

96. 发明授权

US07348259B2 Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers 有权
标题翻译：制造半导体结构的方法，其包括将一个或多个材料层转移到基底并使至少一个材料层的暴露表面平滑
公开(公告)号：US07348259B2
公开(公告)日：2008-03-25
申请号：US11028248
申请日：2005-01-03
申请人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri A. Antoniadis
发明人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri A. Antoniadis
IPC分类号： H01L21/461
CPC分类号： H01L21/76256 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/30608
摘要： A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop S1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed Si1-yGey layer, strained Si1-zGez layer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.
摘要翻译：一种制造半导体结构的方法。根据本发明的一个方面，在第一半导体衬底上沉积第一组分梯度的Si 1-x N Ge x N x缓冲层，其中Ge组合物x从约零到小于约20％的值。然后沉积第一蚀刻停止Si 1-y Ge层，其中Ge组分y大于约20％，使得该层是有效的蚀刻停止。然后生长第二蚀刻停止层的应变Si。沉积层结合到第二衬底。之后，移除第一衬底以释放所述第一蚀刻停止层1-y层。然后在另一步骤中除去剩余的结构以释放第二蚀刻停止层。根据本发明的另一方面，提供一种半导体结构。该结构具有要形成半导体器件的层。半导体结构包括衬底，绝缘层，Ge组分大于约15％的弛豫SiGe层，以及选自但不限于应变Si，弛豫Si

97. 发明授权

US07304336B2 FinFET structure and method to make the same 有权
标题翻译： FinFET结构和方法制作相同
公开(公告)号：US07304336B2
公开(公告)日：2007-12-04
申请号：US10778953
申请日：2004-02-13
申请人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
发明人： Zhiyuan Cheng , Eugene A. Fitzgerald , Dimitri Antoniadis
IPC分类号： H01L29/76 , H01L29/32
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

98. 发明授权

US07301180B2 Structure and method for a high-speed semiconductor device having a Ge channel layer 有权
标题翻译：具有Ge沟道层的高速半导体器件的结构和方法
公开(公告)号：US07301180B2
公开(公告)日：2007-11-27
申请号：US10173986
申请日：2002-06-18
申请人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
发明人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
IPC分类号： H01L31/0328
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/78684
摘要： The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.
摘要翻译：本发明提供包括应变Ge沟道层的半导体结构和设置在应变Ge沟道层上的栅极电介质。在本发明的一个方面，提供了应变的Ge沟道MOSFET。应变Ge沟道MOSFET包括Ge含量在50-95％之间的弛豫SiGe虚拟衬底和形成在虚拟衬底上的应变Ge沟道。在应变Ge通道上形成栅极结构，于是形成具有在体积Si上增加的性能的MOSFET。在本发明的另一实施例中，包括松弛的Ge沟道层和虚拟衬底的半导体结构，其中放宽的Ge沟道层设置在虚拟衬底之上。在本发明的另一方面，提供了一种放宽的Ge沟道MOSFET。该方法包括提供具有约100％的Ge组成的松弛虚拟衬底和形成在虚拟衬底上的松弛Ge沟道。

99. 发明授权

US07202124B2 Strained gettering layers for semiconductor processes 失效
标题翻译：用于半导体工艺的应变吸收层
公开(公告)号：US07202124B2
公开(公告)日：2007-04-10
申请号：US10956481
申请日：2004-10-01
申请人： Eugene A. Fitzgerald , Arthur J. Pitera
发明人： Eugene A. Fitzgerald , Arthur J. Pitera
IPC分类号： H01L21/8238 , H01L21/322
CPC分类号： H01L21/26506 , C30B25/20 , C30B33/00 , H01L21/3221 , H01L21/3226 , H01L21/76254
摘要： A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a particle-confining region proximate the tensilely strained layer. The method also includes introducing particles into the donor wafer to a depth below the surface, and accumulating at least some particles within the tensilely strained gettering layer. Next, the method includes initiating a cleaving action so as to separate at least one of the material layers form the substrate. The tensilely strained gettering layer may accumulate particles and/or point defects and reduce the implantation dose and thermal budget required for cleaving.
摘要翻译：使用拉伸应变吸气层形成半导体结构的方法和结构。该方法包括形成供体晶片，其包括设置在基板上方的拉伸变应的吸气层，以及设置在拉伸变应的吸气层上的至少一个材料层。此外，施主晶片可以具有靠近拉伸应变层的颗粒约束区域。该方法还包括将颗粒引入供体晶片到表面下方的深度，并且在拉伸变应的吸气层内积聚至少一些颗粒。接下来，该方法包括引发切割动作，以将至少一个材料层分离成基底。拉伸应变吸气层可能会积聚颗粒和/或点缺陷，并减少切割所需的注射剂量和热预算。

100. 发明授权

US07138649B2 Dual-channel CMOS transistors with differentially strained channels 有权
公开(公告)号：US07138649B2
公开(公告)日：2006-11-21
申请号：US10164665
申请日：2002-06-07
申请人： Matthew T. Currie , Anthony J. Lochtefeld , Eugene A. Fitzgerald
发明人： Matthew T. Currie , Anthony J. Lochtefeld , Eugene A. Fitzgerald
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/823807 , H01L21/823412 , H01L27/0922
摘要： A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式