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91. 发明授权

US07265376B2 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US07265376B2
公开(公告)日：2007-09-04
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L35/24 , H01L51/00 , H01L29/788 , H01L21/336
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入电绝缘层中的电荷载流子的影响。

92. 发明授权

US07214582B2 Semiconductor substrate and semiconductor circuit formed therein and fabrication methods 有权
标题翻译：其中形成半导体衬底和半导体电路及其制造方法
公开(公告)号：US07214582B2
公开(公告)日：2007-05-08
申请号：US10523944
申请日：2003-09-13
申请人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rösner , Michael Specht
发明人： Franz Hofmann , Volker Lehmann , Lothar Risoh , Wolfgang Rösner , Michael Specht
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10832 , H01L27/10867 , H01L27/1203 , H01L28/82 , H01L29/66181 , H01L29/945
摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.
摘要翻译：提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

93. 发明授权

US07208794B2 High-density NROM-FINFET 失效
标题翻译：高密度NROM-FINFET
公开(公告)号：US07208794B2
公开(公告)日：2007-04-24
申请号：US11073017
申请日：2005-03-04
申请人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Johannes Luyken , Wolfgang Roesner , Michael Specht
IPC分类号： H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/119
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.
摘要翻译：具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中，肋骨肋具有基本上矩形的形状，肋的上侧和肋侧面相对。存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

94. 发明授权

US07030434B1 Arrangement with image sensors 有权
标题翻译：图像传感器布置
公开(公告)号：US07030434B1
公开(公告)日：2006-04-18
申请号：US10089570
申请日：2000-09-28
申请人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
发明人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14609
摘要： A memory transistor and a selection transistor of an image sensor are connected in series and between a bit line (B5) and a reference line (R5). A gate electrode of the selection transistor is connected to a word line (W5), which extends crosswise in relation to the bit line (B5). A diode of the image sensor is switched between a gate electrode (G5) of the memory transistor and a first source/drain area (S/D5) of the memory transistor, which is connected to the selection transistor in such a way is polarized towards the first source/drain area (S/D5) of the memory transistor and in the reverse direction. A photodiode of the image sensor is switched between a voltage connection and either the gate electrode (G5) of the memory transistor or the first source/drain area (S/D5) of the memory transistor in such a way that it is polarized towards the voltage connection and in the reverse direction.
摘要翻译：图像传感器的存储晶体管和选择晶体管串联连接在位线（B 5）和基准线（R 5）之间。选择晶体管的栅电极连接到相对于位线（B 5）横向延伸的字线（W 5）。图像传感器的二极管在存储晶体管的栅电极（G 5）和存储晶体管的第一源极/漏极区域（S / D 5）之间切换，以这样的方式连接到选择晶体管朝向存储晶体管的第一源极/漏极区域（S / D 5）偏振并且沿相反方向偏振。图像传感器的光电二极管在存储晶体管的栅电极（G 5）或存储晶体管的第一源/漏区（S / D 5）的电压连接和栅极之间切换，使得其被极化朝向电压连接和相反方向。

95. 发明授权

US06798014B2 Semiconductor memory cell and semiconductor component as well as manufacturing methods therefore 失效
标题翻译：因此，半导体存储单元和半导体元件以及制造方法
公开(公告)号：US06798014B2
公开(公告)日：2004-09-28
申请号：US10140393
申请日：2002-05-07
申请人： Till Schloesser , Franz Hofmann
发明人： Till Schloesser , Franz Hofmann
IPC分类号： H01L29788
CPC分类号： H01L27/108 , G11C11/404 , G11C11/405 , H01L27/10823 , H01L27/10876
摘要： A semiconductor memory cell with a storage transistor, a selection transistor and a layer structure is provided. The layer structure is formed of at least two semiconductor layers separated from one another by a dielectric. A control electrode that controls a current flow through the layer structure is arranged at at least one end face of the layer structure. The layer structure forms what is referred to as a PLED device.
摘要翻译：提供具有存储晶体管，选择晶体管和层结构的半导体存储单元。层结构由通过电介质彼此分离的至少两个半导体层形成。控制电流通过层结构的控制电极设置在层结构的至少一个端面。层结构形成所谓的PLED设备。

96. 发明授权

US06638812B2 Method for producing a memory cell for a semiconductor memory 有权
公开(公告)号：US06638812B2
公开(公告)日：2003-10-28
申请号：US10096459
申请日：2002-03-12
申请人： Till Schlösser , Franz Hofmann
发明人： Till Schlösser , Franz Hofmann
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate and remains as a web during an etching process while a trench is filled with the common opposing electrode of the memory cell array. In the method, it is advantageous for the selection transistor to be in the form of a vertical transistor above the memory node in the freestanding web.

97. 发明授权

US06492221B1 DRAM cell arrangement 有权
标题翻译： DRAM单元布置
公开(公告)号：US06492221B1
公开(公告)日：2002-12-10
申请号：US09806427
申请日：2001-07-03
申请人： Franz Hofmann , Josef Willer , Till Schloesser
发明人： Franz Hofmann , Josef Willer , Till Schloesser
IPC分类号： H01L218244
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word line connects a first set of alternate memory cells of a row by a first subset of the plurality of connecting pillars. The first word line includes first parts arranged offset relative to the first subset of connecting pillars. A strip-shaped second part extends above the main area and adjoins the first parts of the first word line. A second word line connects to a second set of alternate memory cells of the row by a second subset of the connecting pillars. The second word line includes first parts arranged between mutually adjacent first word lines and offset from the second subset of the connecting pillars. Both the first and second word lines thus overlap but do not cover the connecting pillars. A strip-shaped second part extends above the main area in the first direction and adjoins the first parts of the second word line. The second part is above the first word line and the bit line.
摘要翻译：动态随机存取存储器包括以衬底上的行和列布置的存储器单元和多个连接柱，每个连接柱与存储单元相关联。位线延伸到基板的主区域上方，并连接到列的每个存储单元。第一字线将一行的第一组备用存储单元与多个连接柱的第一子集连接。第一字线包括相对于连接柱的第一子集排列的第一部分。带状第二部分在主区域的上方延伸并与第一字线的第一部分邻接。第二字线通过连接柱的第二子集连接到该行的第二组替代存储器单元。第二字线包括布置在彼此相邻的第一字线之间的第一部分和与连接柱的第二子集的偏移。因此，第一和第二字线都重叠，但不覆盖连接柱。带状第二部分沿着第一方向延伸到主区域上方并与第二字线的第一部分相邻。第二部分在第一个字线和位线之上。

98. 发明授权

US06448600B1 DRAM cell configuration and fabrication method 失效
标题翻译： DRAM单元配置和制造方法
公开(公告)号：US06448600B1
公开(公告)日：2002-09-10
申请号：US09713484
申请日：2000-11-15
申请人： Till Schlösser , Franz Hofmann , Josef Willer
发明人： Till Schlösser , Franz Hofmann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10876 , H01L27/10888
摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.
摘要翻译：存储单元各自具有电容器和晶体管。电容器的存储节点布置在形成在基板中的第一凹部中。晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。第二凹陷与第一凹陷间隔开。晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。

99. 发明授权

US06442065B1 Method for operating a memory cell configuration having dynamic gain memory cells 有权
标题翻译：用于操作具有动态增益存储单元的存储单元配置的方法
公开(公告)号：US06442065B1
公开(公告)日：2002-08-27
申请号：US09935356
申请日：2001-08-22
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： G11C1140
CPC分类号： G11C11/404 , G11C11/4023
摘要： Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
摘要翻译：单元结构的每个存储单元包括至少一个存储晶体管。为了在存储单元上写入第一或第二信息，对存储晶体管的栅电极进行充电，使得在存储晶体管中施加第一电压或第二电压。在存储晶体管的第二源极/漏极区域中施加读取电压以分别读取第一信息和第二信息。第一电压施加在第二电压和读取电压之间。读取电压施加在较低存储晶体管的阈值电压的第一电压和小于存储晶体管的阈值电压的第二电压之间。

100. 发明授权

US06362502B1 DRAM cell circuit 有权
标题翻译： DRAM单元电路
公开(公告)号：US06362502B1
公开(公告)日：2002-03-26
申请号：US09692118
申请日：2000-10-19
申请人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
发明人： Wolfgang Rösner , Thomas Schulz , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/1203 , H01L27/108 , H01L27/10876
摘要： A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.
摘要翻译：存储单元包含存储晶体管和转移晶体管。转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。控制栅电极通过第二电介质层与浮置栅电极隔离。存储晶体管的第一源/漏区连接到位线。存储器和转移晶体管优选地具有不同的导电类型。在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

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