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91. 发明申请

US20080025392A1 Method and apparatus for controlling video encoding data rate 审中-公开
标题翻译：用于控制视频编码数据速率的方法和装置
公开(公告)号：US20080025392A1
公开(公告)日：2008-01-31
申请号：US11880969
申请日：2007-07-25
申请人： Chang-Hyun Lee , Jae-Seok Kim , Seong-Joo Lee , Yun-Je Oh , Young-Hun Joo
发明人： Chang-Hyun Lee , Jae-Seok Kim , Seong-Joo Lee , Yun-Je Oh , Young-Hun Joo
IPC分类号： H04N7/26
CPC分类号： H04N19/86 , H04N19/115 , H04N19/124 , H04N19/142 , H04N19/61
摘要： A method and apparatus for controlling a video encoding data rate in real-time in order to minimize performance deterioration, even when a scene change has occurred in an application field having a small number of available bits due to a low bit rate and a high frame rate. The method includes: a first step of determining whether scene change has occurred in a current frame; a second step of determining whether a number of current available bits is more than a preset reference when it is determined that the scene change has occurred; and a third step of adjusting a Quantization Parameter (QP) according to a first preset condition when it is determined that the number of current available bits is more than that preset reference. An apparatus includes an encoder QP controller having a QP module for adjusting the QP.
摘要翻译：即使当由于低比特率和高帧而在具有少量可用比特的应用领域中发生场景变化时，也可以实时地控制视频编码数据速率以便最小化性能劣化的方法和装置率。该方法包括：确定在当前帧中是否发生场景变化的第一步骤; 当确定出现场景变化时，确定当前可用位数是否大于预设参考值的第二步骤; 以及当确定当前可用位的数量大于该预设参考值时，根据第一预设条件调整量化参数（QP）的第三步骤。一种装置包括具有用于调整QP的QP模块的编码器QP控制器。

92. 发明授权

US07218863B2 Optical transmission system for optimizing bias of laser diode for SCM analog optical signal 有权
标题翻译：用于优化SCM模拟光信号激光二极管偏置的光传输系统
公开(公告)号：US07218863B2
公开(公告)日：2007-05-15
申请号：US10638453
申请日：2003-08-11
申请人： Chang-Hyun Lee , Chan-Yul Kim , Yun-Je Oh , Jun-Ho Koh
发明人： Chang-Hyun Lee , Chan-Yul Kim , Yun-Je Oh , Jun-Ho Koh
IPC分类号： H04B10/04
CPC分类号： H04B10/504 , H04B10/58
摘要： An optical transmission system for optimizing the bias of a laser diode during an SCM analog optical transmission includes an optical transmitter for converting a baseband electric signal into an optical signal using a laser diode according to the set bias and outputting the optical signal through an optical line, an optical receiver for converting the optical signal transmitted from the optical transmitter into the baseband electric signal, a recovery unit for detecting an error generated according to the bias of the laser diode on the basis of the electric signal converted by the optical receiver, and a bias adjuster for optimally adjusting the bias of the laser diode on the basis of a value of the error detected by the reproducer.
摘要翻译：一种用于在SCM模拟光传输期间优化激光二极管的偏置的光传输系统包括：光发射机，用于根据设定的偏置，使用激光二极管将基带电信号转换为光信号，并通过光线路输出光信号用于将从光发送器发送的光信号转换为基带电信号的光接收器，用于根据由光接收器转换的电信号来检测根据激光二极管的偏置产生的误差的恢复单元;以及偏置调节器，用于基于由再现器检测到的误差的值来最佳地调整激光二极管的偏置。

93. 发明授权

US07157762B2 Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices 有权
标题翻译：具有改进的栅极绝缘层的半导体器件和制造这种器件的相关方法
公开(公告)号：US07157762B2
公开(公告)日：2007-01-02
申请号：US10982580
申请日：2004-11-04
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/42324
摘要： Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls defines a peripheral active region in the peripheral circuit region. A cell gate pattern that includes a plurality of conductive layers crosses over the cell active region, and a peripheral gate pattern that includes a plurality of conductive layers crosses over the peripheral active region. A lowermost layer of the peripheral gate pattern has first and second sidewalls that are aligned with respective of either the first and second sidewalls of the second device isolation layer or a vertical extension of the first and second sidewalls of the second device isolation layer. Further, the lowest layer of the cell gate pattern and the lowest layer of the peripheral gate pattern comprise different conductive layers.
摘要翻译：半导体器件设置在具有单元阵列区域和外围电路区域的基板上。第一器件隔离层限定电池阵列区域中的电池有源区，并且具有第一和第二侧壁的第二器件隔离层限定外围电路区域中的外围有源区。包括多个导电层的单元栅极图案与单元有源区交叉，并且包括多个导电层的外围栅极图案跨过周边有源区。外围栅极图案的最下层具有与第二器件隔离层的第一和第二侧壁的相应的第一和第二侧壁或第二器件隔离层的第一和第二侧壁的垂直延伸部对准的第一和第二侧壁。此外，单元栅极图案的最下层和外围栅极图案的最下层包括不同的导电层。

94. 发明申请

US20060261398A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20060261398A1
公开(公告)日：2006-11-23
申请号：US11434175
申请日：2006-05-16
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L28/20 , H01L29/4232
摘要： Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode includes stacked semiconductor layers. The conductive layer of the cell gate electrode is different from the lowest semiconductor layer of the peripheral gate electrode in material, which can improve characteristics of memory cells and peripheral transistors without causing mutual interference with each other.
摘要翻译：公开了一种具有限制在基板上的单元和外围电路区域的非易失性存储器件。电池栅电极配置在电池区域，而周边电极配置在外围电路区域。每个单元栅极电极包括堆叠的导电和半导体层，但是外围栅电极包括堆叠的半导体层。单元栅电极的导电层与材料中外围栅电极的最低半导体层不同，这可以改善存储单元和外围晶体管的特性，而不会相互干扰。

95. 发明授权

US07132331B2 Non-volatile semiconductor memory devices having self-aligned gate conductive layers and methods of fabricating such devices 失效
标题翻译：具有自对准栅极导电层的非易失性半导体存储器件及其制造方法
公开(公告)号：US07132331B2
公开(公告)日：2006-11-07
申请号：US10990903
申请日：2004-11-17
申请人： Young-Goan Jang , Chang-Hyun Lee , Jae-Hoon Kim
发明人： Young-Goan Jang , Chang-Hyun Lee , Jae-Hoon Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76229 , H01L21/823481 , H01L27/115
摘要： A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of the field isolation patterns is then increased by, for example, a thermal annealing process. A plurality of gate insulation patterns are then formed on respective of the active regions. A plurality of first conductive patterns are then formed on respective of the gate insulation patterns.
摘要翻译：公开了具有自对准栅极导电层的半导体器件及其制造方法。在本发明的实施例中，在半导体衬底上形成多个场隔离图案以在半导体衬底中限定多个有源区。然后通过例如热退火工艺增加场隔离图案的密度。然后在相应的有源区上形成多个栅极绝缘图案。然后在相应的栅极绝缘图案上形成多个第一导电图案。

96. 发明申请

US20060240612A1 Non-Volatile Memory Devices with Charge Storage Insulators and Methods of Fabricating Such Devices 有权
标题翻译：具有充电存储绝缘体的非易失性存储器件和制造这种器件的方法
公开(公告)号：US20060240612A1
公开(公告)日：2006-10-26
申请号：US11428884
申请日：2006-07-06
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines. The conductive patterns penetrate the charge storage insulator and electrically connect with the active regions.
摘要翻译：非易失性存储器件包括限定在衬底处的单元区域和形成在单元区域中以限定多个有源区域的多个器件隔离层。电荷存储绝缘体基本上覆盖电池区域的整个顶表面。在电荷存储绝缘体上形成有跨越器件隔离层的多条栅极线。导电图案设置在穿过电荷存储绝缘体的预定栅极线之间以与有源区电连接。根据该器件的制造方法，在衬底中形成多个器件隔离层，然后在衬底和器件隔离层的整个表面上形成电荷存储绝缘体。在电荷存储绝缘体上形成跨越器件隔离层的多条平行栅极线，然后在预定栅极线之间形成导电图案。导电图案穿透电荷存储绝缘体并与有源区电连接。

97. 发明申请

US20060208338A1 Nonvolatile memory devices and methods of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20060208338A1
公开(公告)日：2006-09-21
申请号：US11375983
申请日：2006-03-15
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

98. 发明申请

US20060202263A1 Nonvolatile semiconductor memory device and method of fabricating the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060202263A1
公开(公告)日：2006-09-14
申请号：US11296479
申请日：2005-12-08
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： In an example embodiment, a semiconductor substrate has a plurality of active regions separated by a plurality of trenches. A gate insulation film fills at least a portion of the trenches, and a conductive gate film is formed over the gate insulation film. In an example embodiment, the gate insulation film, may include a tunneling insulation film, a charge storage film, and a blocking insulation film. The example embodiment may also include field isolation films, which partially fill the trenches of the semiconductor substrate, such that the upper surfaces of the active regions or the substrate are higher than the upper surfaces of the field isolation films.
摘要翻译：在示例性实施例中，半导体衬底具有由多个沟槽分隔开的多个有源区域。栅极绝缘膜填充沟槽的至少一部分，并且在栅极绝缘膜上形成导电栅极膜。在示例性实施例中，栅极绝缘膜可以包括隧道绝缘膜，电荷存储膜和阻挡绝缘膜。示例实施例还可以包括场隔离膜，其部分地填充半导体衬底的沟槽，使得有源区或衬底的上表面高于场隔离膜的上表面。

99. 发明授权

US06995424B2 Non-volatile memory devices with charge storage insulators 有权
标题翻译：具有电荷存储绝缘体的非易失性存储器件
公开(公告)号：US06995424B2
公开(公告)日：2006-02-07
申请号：US10712426
申请日：2003-11-13
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/66833
摘要： A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines. The conductive patterns penetrate the charge storage insulator and electrically connect with the active regions.
摘要翻译：非易失性存储器件包括限定在衬底处的单元区域和形成在单元区域中以限定多个有源区域的多个器件隔离层。电荷存储绝缘体基本上覆盖电池区域的整个顶表面。在电荷存储绝缘体上形成有跨越器件隔离层的多条栅极线。导电图案设置在穿过电荷存储绝缘体的预定栅极线之间以与有源区电连接。根据该器件的制造方法，在衬底中形成多个器件隔离层，然后在衬底和器件隔离层的整个表面上形成电荷存储绝缘体。在电荷存储绝缘体上形成跨越器件隔离层的多条平行栅极线，然后在预定栅极线之间形成导电图案。导电图案穿透电荷存储绝缘体并与有源区电连接。

100. 发明授权

US06987694B2 Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices 有权
标题翻译：编程非易失性半导体存储器件包括耦合电压和相关器件的方法
公开(公告)号：US06987694B2
公开(公告)日：2006-01-17
申请号：US10640082
申请日：2003-08-13
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： G11C16/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/3418
摘要： A non-volatile memory device may include a string of serially connected memory cell transistors with each memory cell transistor of the string being connected to a different word line. The non-volatile memory device may be programmed by applying a pass voltage to a first word line connected to a first memory cell transistor of the string, by applying a coupling voltage to a second word line connected to a second memory cell transistor of the string, and by applying a program voltage to a third word line connected to a third memory cell transistor of the string. More particularly, the coupling voltage can be greater than a ground voltage of the memory device, and the pass voltage and the coupling voltage can be different. In addition, the program voltage can be applied to the third word line while applying the pass voltage to the first word line and while applying the coupling voltage to the second word line, and the third memory cell transistor can be programmed responsive to applying the program voltage to the third word line wherein the second memory cell transistor is between the first and third memory cell transistors of the serially connected string. Related devices are also discussed.
摘要翻译：非易失性存储器件可以包括一串串联的存储单元晶体管，其中串的每个存储单元晶体管连接到不同的字线。可以通过向连接到串的第一存储单元晶体管的第一字线施加通过电压来对非易失性存储器件进行编程，通过向连接到串的第二存储单元晶体管的第二字线施加耦合电压并且通过对连接到串的第三存储单元晶体管的第三字线施加编程电压。更具体地，耦合电压可以大于存储器件的接地电压，并且通过电压和耦合电压可以不同。此外，可以将编程电压施加到第三字线，同时将通过电压施加到第一字线，同时将耦合电压施加到第二字线，并且第三存储单元晶体管可以响应于应用程序而被编程电压到第三字线，其中第二存储单元晶体管位于串行连接的串的第一和第三存储单元晶体管之间。还讨论了相关设备。

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