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91. 发明授权

US06961876B2 Automatic handling of link failures 有权
标题翻译：自动处理链路故障
公开(公告)号：US06961876B2
公开(公告)日：2005-11-01
申请号：US09961014
申请日：2001-09-21
申请人： Thomas A. Gregg , Stephen R. Burrow , Kulwant M. Pandey , Patrick J. Sugrue
发明人： Thomas A. Gregg , Stephen R. Burrow , Kulwant M. Pandey , Patrick J. Sugrue
IPC分类号： H04L1/22 , G06F11/00
CPC分类号： H04L1/22
摘要： A method and system for I/O adapters that must rely on a central processor to handle all inbound link events to reduce the number of events signaled to the central processor with hardware state machines that sort out the significant link events and automatically generate the appropriate response on the outbound link thereby greatly reducing the central processor utilization. As optical links fail (unplugging the link is a failure) or when receiving multiple continuous sequences, numerous events must be filtered by the hardware state machines to limit the number of interrupts presented to the central processor.
摘要翻译：一种用于I / O适配器的方法和系统，其必须依赖于中央处理器来处理所有入站链路事件，以减少用硬件状态机向中央处理器发出信号的事件数，该硬件状态机对整个重要链路事件进行整理，并自动生成适当的响应在出站链路上，从而大大降低了中央处理器的利用率。由于光链路故障（拔掉链路是故障）或者当接收到多个连续序列时，硬件状态机必须对多个事件进行过滤，以限制呈现给中央处理器的中断次数。

92. 发明授权

US06693880B2 System of controlling the flow of information between senders and receivers across links being used as channels 有权
标题翻译：控制发送者和接收者之间信息流的系统被用作通道
公开(公告)号：US06693880B2
公开(公告)日：2004-02-17
申请号：US09885608
申请日：2001-06-20
申请人： Thomas A. Gregg , Kulwant M. Pandey
发明人： Thomas A. Gregg , Kulwant M. Pandey
IPC分类号： G01R3108
CPC分类号： H04L47/10 , H04L47/34
摘要： Controlling the flow of information between senders and receivers across links being used as channels. In one example, a self-timed interface link is adapted to be used as a channel. Such an interface is referred to as an integrated cluster bus. The flow control for the integrated cluster bus includes, for instance, a Data Request packet that indicates to the transmitter of data that it can now send the data; a continue indicator that specifies that more data is to follow; and a sequence indicator that is used to determine if a particular message is in proper sequence order. The integrated cluster bus does not require large data buffers and offers low latency messaging.
摘要翻译：控制作为通道使用的链路之间的发送者和接收者之间的信息流。在一个示例中，自定义接口链路适于用作信道。这种接口被称为集成集群总线。集成集群总线的流量控制包括例如数据请求分组，其向发射机指示其现在可以发送数据的数据; 一个指示更多数据遵循的继续指标; 以及用于确定特定消息是否处于正确顺序的序列指示符。集成集群总线不需要大数据缓冲区，并提供低延迟消息传递。

93. 发明授权

US5559963A Suspending, resuming, and interleaving frame-groups 失效
标题翻译：挂起，恢复和交织帧组
公开(公告)号：US5559963A
公开(公告)日：1996-09-24
申请号：US148113
申请日：1993-11-04
申请人： Thomas A. Gregg , Joseph M. Hoke , Kulwant M. Pandey
发明人： Thomas A. Gregg , Joseph M. Hoke , Kulwant M. Pandey
IPC分类号： H04L29/00 , H04J3/06 , H04L25/02 , H04L29/06 , H04L29/14 , H04L5/00 , H04L7/00
CPC分类号： H04J3/0629 , H04L69/14 , H04L69/40 , Y02B60/33
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups can be prematurely ended on any 256 byte block boundary for several purposes, and all the frames of a given group must contain the same number of information field data words. Allowing frame groups to be ended on arbitrary block boundaries allows their transmission to start before all of the information field for the frame group has been received from a shared main processor storage. This capability of ending frame groups also allows high priority frame groups to interrupt the transmission of a relatively long data frame. Finally, the capability to end the frame group protects the information field of a stalled frame group since the CRC is sent and the idle sequence is resumed. Using multiple, independently clocked transmitters improves the fault tolerance of the link but also makes it difficult to end all frame of the frame group on the same block boundary. This problem is also solved by keeping track of the data sent to the multiple transmit buffers.
摘要翻译：一种以串行方式跨多个光纤并行传输数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。为了多个目的，帧组可以在任何256字节块边界上过早地结束，并且给定组的所有帧必须包含相同数量的信息字段数据字。允许帧组在任意块边界上结束允许它们在从共享主处理器存储器接收到所有帧组的所有信息字段之前开始传输。结束帧组的这种能力还允许高优先级帧组中断相对长的数据帧的传输。最后，结束帧组的能力保护失速帧组的信息字段，因为CRC被发送并且空闲序列被恢复。使用多个独立时钟的发射机提高了链路的容错能力，也使得难以在同一块边界上结束帧组的所有帧。通过跟踪发送到多个发送缓冲区的数据来解决这个问题。

94. 发明授权

US5425020A Skew measurement for receiving frame-groups 失效
标题翻译：接收帧组的倾斜测量
公开(公告)号：US5425020A
公开(公告)日：1995-06-13
申请号：US147701
申请日：1993-11-04
申请人： Thomas A. Gregg , Joseph M. Hoke , Patrick J. Sugrue
发明人： Thomas A. Gregg , Joseph M. Hoke , Patrick J. Sugrue
IPC分类号： H04J14/08 , H04L25/14 , H04J3/14
CPC分类号： H04L25/14 , H04J14/08
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. The transceivers for each member of the parallel bus asynchronously achieve synchronism from either end of the fiber. A receiver of a transceiver determines a relative skew on a conductor of a link by performing skew measurements on a series of calibration frames sent by a transmitter on another end of said link. A skew monitor performs skew measurements and includes a plurality of skew measurement registers for measuring the relative skew between frames of a frame group, each register having an input from a skew counter, and outputs coupled to a microprocessor controlling the monitor. Each register gates in the value in the skew counter at the time a link control word is received. The receiver can determine that one or more frames of the calibration frames have been lost and have not exceeded the maximum measureable skew limits.
摘要翻译：一种以串行方式跨多个光纤并行传输数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。帧组不具有序列号，因此，接收机根据各个帧的到达时间确定哪些帧是帧组的一部分。并行总线的每个成员的收发器异步地实现了光纤任一端的同步。收发器的接收机通过在由所述链路的另一端上的发射机发送的一系列校准帧上执行偏移测量来确定链路的导体上的相对偏斜。偏斜监视器执行偏斜测量并且包括多个偏斜测量寄存器，用于测量帧组的帧之间的相对偏差，每个寄存器具有来自偏斜计数器的输入，以及耦合到控制监视器的微处理器的输出。每个寄存器在接收到链路控制字时在偏移计数器的值中进行门控。接收机可以确定校准帧的一个或多个帧已经丢失并且没有超过最大可测量偏斜极限。

95. 发明授权

US5267240A Frame-group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5267240A
公开(公告)日：1993-11-30
申请号：US839986
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
IPC分类号： H04L29/00 , H04J3/06 , H04L25/02 , H04L29/06 , H04L29/14 , G06K5/04
CPC分类号： H04J3/0629 , H04L69/14 , H04L69/40 , Y02B60/33
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

96. 发明授权

US5101477A System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers 失效
标题翻译：用于通道和具有请求和备份请求计数寄存器的输入/输出设备之间的数据帧的高速传输系统
公开(公告)号：US5101477A
公开(公告)日：1992-03-31
申请号：US481071
申请日：1990-02-16
申请人： Daniel F. Casper , John R. Flanagan , Thomas A. Gregg , Catherine C. Huang , Matthew J. Kalos
发明人： Daniel F. Casper , John R. Flanagan , Thomas A. Gregg , Catherine C. Huang , Matthew J. Kalos
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： A data transfer apparatus for use in transferring data frames between a data buffer and an input/out (I/O) device in a data processing system. A channel in the data processing system includes an inbound frame header buffer for storing a header from an inbound data frame from the I/O device, an outbound frame header buffer for building a header for an outbound data frame to be sent to the I/O device, a data buffer for storing data transmitted between the data processing system and the I/O device, and a data transfer control circuit for controlling the number of data bytes to be transferred between the data buffer and the I/O device. The channel also includes a microcode routine controlled microprocessor for analyzing frame headers in the inbound frame header buffer, for building frame headers in the outbound frame header buffer, for initiating the transmission of outbound frames, and for controlling the data transfer control circuit for transferring a desired number of data bytes.

97. 发明授权

US08737228B2 Flow control management in a data center ethernet network over an extended distance 有权
标题翻译：数据中心以太网网络中的流量控制管理延长了距离
公开(公告)号：US08737228B2
公开(公告)日：2014-05-27
申请号：US11862664
申请日：2007-09-27
申请人： Casimer DeCusatis , Thomas A. Gregg
发明人： Casimer DeCusatis , Thomas A. Gregg
IPC分类号： H04L1/00 , H04L12/56
CPC分类号： H04L47/215 , H04L47/10 , H04L47/13 , H04L47/21 , H04L47/30 , H04L47/39
摘要： Flow control in a data center Ethernet (DCE) network is managed between a source node and a destination node separated by an extended distance. An initiation sequence between the source node and the destination node is intercepted. The imitation sequence is for determining buffer credits available for receiving packets in the source node and the destination node. Replies are generated to the source node and the destination node indicating buffer credits available in at least one extended data interface interspersed between the source node and the destination node. The initiation sequence is completed based on the replies from the extended data interface.
摘要翻译：数据中心的流量控制以太网（DCE）网络在源节点和目的节点之间进行管理，间隔一段距离。源节点和目的节点之间的启动序列被拦截。模拟序列用于确定可用于在源节点和目的地节点中接收分组的缓冲区信用。生成对源节点和目的地节点的指示，指示在源节点和目的地节点之间散布的至少一个扩展数据接口中可用的缓冲区信用。启动顺序是根据扩展数据接口的回复完成的。

98. 发明授权

US08683108B2 Connected input/output hub management 失效
标题翻译：连接的输入/输出集线器管理
公开(公告)号：US08683108B2
公开(公告)日：2014-03-25
申请号：US12821248
申请日：2010-06-23
申请人： Gerd K. Bayer , Beth A. Glendening , Thomas A. Gregg , Michael Jung , Elke G. Nass , Peter K. Szwed
发明人： Gerd K. Bayer , Beth A. Glendening , Thomas A. Gregg , Michael Jung , Elke G. Nass , Peter K. Szwed
IPC分类号： G06F13/36
CPC分类号： G06F13/385
摘要： A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.
摘要翻译：用于实现连接的输入/输出（I / O）集线器配置和管理的方法包括：利用第二I / O集线器在包装模式下配置第一I / O集线器。集线器通过绕线电缆进行通信耦合。该方法还包括在包括集线器的计算子系统上生成数据业务。生成流量包括：通过第一集线器将实现交易的请求转换成I / O设备可读请求分组，并通过包络线传输请求分组; 通过第二集线器将I / O设备可读（IODR）请求分组转换成系统可读请求，并通过系统总线发送请求; 经由第二集线器转换对IODR响应分组的响应，以及通过所述线缆传输所述响应分组; 以及经由所述第一集线器将所述IODR响应分组转换为系统可读应答分组，以及通过所述系统总线发送所述响应分组。

99. 发明授权

US08656375B2 Cross-logical entity accelerators 有权
标题翻译：跨逻辑实体加速器
公开(公告)号：US08656375B2
公开(公告)日：2014-02-18
申请号：US12610583
申请日：2009-11-02
申请人： Rajaram B. Krishnamurthy , Thomas A. Gregg
发明人： Rajaram B. Krishnamurthy , Thomas A. Gregg
IPC分类号： G06F9/45 , G06F15/16 , G06F9/00
CPC分类号： G06F9/5077
摘要： A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.
摘要翻译：创建跨逻辑实体组，其包括要由多个逻辑实体共享的一个或多个加速器。加速器上的实例是多个逻辑实体中通用的功能。要实例化的功能例如在运行时动态地确定。

100. 发明授权

US08510509B2 Data transfer to memory over an input/output (I/O) interconnect 有权
标题翻译：通过输入/输出（I / O）互连将数据传输到存储器
公开(公告)号：US08510509B2
公开(公告)日：2013-08-13
申请号：US11958418
申请日：2007-12-18
申请人： Thomas A. Gregg , Rajaram B. Krishnamurthy
发明人： Thomas A. Gregg , Rajaram B. Krishnamurthy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0835 , G06F12/0806 , G06F12/0888 , G06F2212/1021 , G06F2212/507 , G06F2212/621
摘要： A method, system, and computer program product for data transfer to memory over an input/output (I/O) interconnect are provided. The method includes reading a mailbox stored on an I/O adapter in response to a request to initiate an I/O transaction. The mailbox stores a directive that defines a condition under which cache injection for data values in the I/O transaction will not be performed. The method also includes embedding a hint into the I/O transaction when the directive in the mailbox matches data received in the request, and executing the I/O transaction. The execution of the I/O transaction causes a system chipset or I/O hub for a processor receiving the I/O transaction, to directly store the data values from the I/O transaction into system memory and to suppress the cache injection of the data values into a cache memory upon presence of the hint in a header of the I/O transaction.
摘要翻译：提供了一种用于通过输入/输出（I / O）互连将数据传输到存储器的方法，系统和计算机程序产品。该方法包括响应于发起I / O事务的请求读取存储在I / O适配器上的邮箱。邮箱存储一个指令，定义了一个条件，在该条件下，不会执行I / O事务中的数据值的高速缓存注入。该方法还包括在邮箱中的指令与请求中接收的数据匹配并执行I / O事务时，将提示嵌入到I / O事务中。执行I / O事务导致接收I / O事务的处理器的系统芯片组或I / O集线器将来自I / O事务的数据值直接存储到系统存储器中，并且抑制高速缓存注入在I / O事务的头部存在提示时，数据值进入高速缓冲存储器。

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