专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20130119539A1 Package Structures and Methods for Forming the Same 有权
标题翻译：包装结构及其形成方法
公开(公告)号：US20130119539A1
公开(公告)日：2013-05-16
申请号：US13298102
申请日：2011-11-16
申请人： Ching-Wen Hsiao , Ming-Da Cheng , Chih-Wei Lin , Chen-Shien Chen , Chih-Hua Chen , Chen-Cheng Kuo
发明人： Ching-Wen Hsiao , Ming-Da Cheng , Chih-Wei Lin , Chen-Shien Chen , Chih-Hua Chen , Chen-Cheng Kuo
IPC分类号： H05K1/11 , H01L21/60 , H01L23/485
CPC分类号： H01L23/49816 , H01L21/6835 , H01L23/3128 , H01L23/49822 , H01L24/16 , H01L25/105 , H01L2221/68318 , H01L2221/68345 , H01L2221/68381 , H01L2224/131 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/014 , H01L2924/00
摘要： A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.
摘要翻译：一种装置包括再分布线，以及在再分配线上模制的聚合物区域。聚合物区域包括第一平坦顶表面。焊料区域设置在聚合物区域中并电耦合到再分配线路。焊料区域包括不高于第一平坦顶表面的第二平坦顶表面。

92. 发明申请

US20130040453A1 Through Silicon Via Layout 有权
标题翻译：通过硅通布局
公开(公告)号：US20130040453A1
公开(公告)日：2013-02-14
申请号：US13653176
申请日：2012-10-16
申请人： Ming-Fa Chen , Chen-Shien Chen
发明人： Ming-Fa Chen , Chen-Shien Chen
IPC分类号： H01L21/768
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/6836 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2221/68327 , H01L2221/68372 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2224/05552
摘要： A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.
摘要翻译：公开了一种用于形成凹凸金属化层的系统和方法，其通过硅通孔和迹线减少了UBM的总占地面积。优选实施例包括在多个通孔上形成凸起下金属化层，而UBM仅连接到其所位于的硅通孔总数的一部分。连接到贯通硅通孔的迹线可另外形成在UBM之下，以在模具表面上节省更多的空间。

93. 发明授权

US08193639B2 Dummy metal design for packaging structures 有权
标题翻译：用于包装结构的虚拟金属设计
公开(公告)号：US08193639B2
公开(公告)日：2012-06-05
申请号：US12750468
申请日：2010-03-30
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L23/485
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
摘要翻译：集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。金属凸块形成在UBM上并与UBM电连接。在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

94. 发明授权

US08097953B2 Three-dimensional integrated circuit stacking-joint interface structure 有权
标题翻译：三维集成电路堆叠接口结构
公开(公告)号：US08097953B2
公开(公告)日：2012-01-17
申请号：US12259879
申请日：2008-10-28
申请人： Ming-Hong Tseng , Kai-Ming Ching , Chen-Shien Chen , Ching-Wen Hsiao , Hon-Lin Huang , Tsung-Ding Wang
发明人： Ming-Hong Tseng , Kai-Ming Ching , Chen-Shien Chen , Ching-Wen Hsiao , Hon-Lin Huang , Tsung-Ding Wang
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05568 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/01019 , H01L2924/01322 , H01L2924/01327 , H01L2924/15311 , H01L2924/00
摘要： A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.
摘要翻译：提出了一种制造叠层半导体衬底的系统，结构和方法。第一基板包括第一侧和第二侧。贯穿基板通孔（TSV）从第一基板的第一侧突出。 TSV的第一突出部分具有导电保护涂层，并且TSV的第二突出部分具有隔离衬垫。该系统还包括在TSV的第一突出部分的导电保护涂层处将第二衬底与第一衬底结合的第二衬底和接合界面结构。

95. 发明申请

US20110291262A1 Strength of Micro-Bump Joints 有权
标题翻译：微型接头的强度
公开(公告)号：US20110291262A1
公开(公告)日：2011-12-01
申请号：US12789696
申请日：2010-05-28
申请人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Ming-Fa Chen , Rung-De Wang
发明人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Ming-Fa Chen , Rung-De Wang
IPC分类号： H01L23/498 , B32B3/10 , B32B15/04 , B32B3/30
CPC分类号： H01L24/16 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/03614 , H01L2224/0401 , H01L2224/05017 , H01L2224/05023 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/1146 , H01L2224/11823 , H01L2224/11831 , H01L2224/1191 , H01L2224/13005 , H01L2224/13018 , H01L2224/13019 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/1369 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/81193 , H01L2224/81345 , H01L2224/81801 , H01L2224/81815 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/35 , Y10T428/12361 , Y10T428/12396 , H01L2924/00 , H01L2924/00012 , H01L2924/01047 , H01L2924/206 , H01L2224/05552
摘要： A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.
摘要翻译：一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。金属凸块和电介质层部分的表面形成界面。在金属凸块上方形成金属涂层并与金属凸块接触。金属表面从介电层上延伸到界面的下方。

96. 发明申请

US20110193220A1 Pillar Structure having a Non-Planar Surface for Semiconductor Devices 有权
标题翻译：具有用于半导体器件的非平面表面的柱结构
公开(公告)号：US20110193220A1
公开(公告)日：2011-08-11
申请号：US12704183
申请日：2010-02-11
申请人： Tin-Hao Kuo , Chen-Shien Chen , Ching-Wen Hsiao
发明人： Tin-Hao Kuo , Chen-Shien Chen , Ching-Wen Hsiao
IPC分类号： H01L23/498 , H01L21/3205
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/13016 , H01L2224/13018 , H01L2224/13022 , H01L2224/13076 , H01L2224/1308 , H01L2224/13084 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/16507 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
摘要翻译：提供了一种用于半导体器件的导电柱。导电柱形成为使得顶表面是非平面的。在实施例中，顶表面可以是凹形，凸形或波浪状。可以在导电柱上形成可选的覆盖层，以允许更强的金属间化合物（IMC）层。 IMC层是在焊料材料和下层之间形成的层，例如导电柱或可选的封盖层。

97. 发明申请

US20110035937A1 Semiconductor Wafer Carrier and Method of Manufacturing 有权
标题翻译：半导体晶圆载体及制造方法
公开(公告)号：US20110035937A1
公开(公告)日：2011-02-17
申请号：US12840903
申请日：2010-07-21
申请人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
发明人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
IPC分类号： H05K13/00
CPC分类号： H01L21/6833 , Y10T29/49124
摘要： A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.
摘要翻译：公开了一种用于半导体晶片载体的系统和方法。一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

98. 发明授权

US07785927B2 Multi-die wafer level packaging 有权
标题翻译：多芯片晶圆级封装
公开(公告)号：US07785927B2
公开(公告)日：2010-08-31
申请号：US12392918
申请日：2009-02-25
申请人： Chen-Shien Chen , Kai-Ming Ching , Chih-Hua Chen , Chen-Cheng Kuo
发明人： Chen-Shien Chen , Kai-Ming Ching , Chih-Hua Chen , Chen-Cheng Kuo
IPC分类号： H01L21/98
CPC分类号： H01L25/0657 , H01L21/563 , H01L21/6835 , H01L21/76898 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/50 , H01L2221/6834 , H01L2221/68381 , H01L2224/0401 , H01L2224/04073 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/2518 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/83102 , H01L2224/83855 , H01L2224/92125 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01016 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/351 , H01L2924/0665 , H01L2924/00 , H01L2224/48145 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.
摘要翻译：提供半导体管芯封装。半导体管芯封装包括以堆叠构造布置的多个管芯。在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

99. 发明申请

US20090269905A1 Tapered Through-Silicon Via Structure 有权
标题翻译：锥形硅通孔结构
公开(公告)号：US20090269905A1
公开(公告)日：2009-10-29
申请号：US12495124
申请日：2009-06-30
申请人： Chen-Shien Chen , Chen-Cheng Kuo , Kai-Ming Ching , Chih-Hua Chen
发明人： Chen-Shien Chen , Chen-Cheng Kuo , Kai-Ming Ching , Chih-Hua Chen
IPC分类号： H01L21/762 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.
摘要翻译：集成电路结构包括：基板; 在衬底中的穿硅通孔（TSV），TSV是锥形的; 从所述基板的顶表面延伸到所述基板中的硬掩模区域，其中所述硬掩模围绕所述TSV的顶部; 衬底上的介电层; 以及从电介质层的顶表面延伸到TSV的金属柱，其中金属柱包括与TSV相同的材料。

100. 发明申请

US20090188104A1 Method of Manufacturing a Coil Inductor 有权
标题翻译：制造线圈电感的方法
公开(公告)号：US20090188104A1
公开(公告)日：2009-07-30
申请号：US12019688
申请日：2008-01-25
申请人： Kai-Ming Ching , Chen-Shien Chen
发明人： Kai-Ming Ching , Chen-Shien Chen
IPC分类号： H01F41/04 , H01F41/02 , H01F41/00
CPC分类号： H01F41/046 , H01F17/0013 , H01F17/0033 , Y10T29/4902
摘要： A method of manufacturing a coil inductor and a coil inductor are provided are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure.
摘要翻译：提供了制造线圈电感器和线圈电感器的方法。多个导电底部结构形成为位于第一介电层上。然后形成多对导电侧结构，其中每对导电侧结构分别位于每个导电底部结构的第一端和第二端的顶表面上; 在第一电介质层上形成第二电介质层，涂覆底部和侧面结构; 并且多个导电顶部结构形成为位于第二介电层上，其中每个导电顶部结构电连接每对导电侧面结构，其中导电底部结构，导电侧面结构和导电顶部结构共同形成导电线圈结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式