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91. 发明授权

US06831363B2 Structure and method for reducing thermo-mechanical stress in stacked vias 有权
标题翻译：用于降低堆叠过孔中热机械应力的结构和方法
公开(公告)号：US06831363B2
公开(公告)日：2004-12-14
申请号：US10319032
申请日：2002-12-12
申请人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76831 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.
摘要翻译：用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

92. 发明授权

US06815813B1 Self-contained heat sink and a method for fabricating same 失效
标题翻译：独立散热片及其制造方法
公开(公告)号：US06815813B1
公开(公告)日：2004-11-09
申请号：US10604211
申请日：2003-07-01
申请人： Timothy J. Dalton , Kevin S. Petrarca , Michelle L. Steen , Cornelia K. Tsang , Richard P. Volant
发明人： Timothy J. Dalton , Kevin S. Petrarca , Michelle L. Steen , Cornelia K. Tsang , Richard P. Volant
IPC分类号： H01L2334
CPC分类号： H01L23/58 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.
摘要翻译：提供了一种从制热电子设备散热的系统和方法。该系统包括用于制造集成电路的基板，该基板具有第一面和第二面。第二面基本上平行于第一面设置，其中设置有电子装置。在电子设备周围的第一面设有金属化的裂纹停止件。多个第一金属导管从其第二面延伸穿过基板到裂缝停止部，其中每个第一金属导管与裂纹停止件热接触以提供从电子装置到第二面的热耗散。

93. 发明授权

US06798029B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06798029B2
公开(公告)日：2004-09-28
申请号：US10434999
申请日：2003-05-09
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2982
CPC分类号： H01H59/0009 , H01H2059/0018 , H01H2059/0072
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

94. 发明授权

US10319870B2 Photovoltaic module with a controllable infrared protection layer 有权
公开(公告)号：US10319870B2
公开(公告)日：2019-06-11
申请号：US12887156
申请日：2010-09-21
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Maxime Darnon , Rainer Krause , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Maxime Darnon , Rainer Krause , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H01L31/00 , H01L31/054 , G02B26/00 , H01L31/048 , H01L31/049
摘要： An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.

95. 发明申请

US20120183743A1 TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL 失效
公开(公告)号：US20120183743A1
公开(公告)日：2012-07-19
申请号：US13432036
申请日：2012-03-28
申请人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
发明人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
IPC分类号： B32B3/30
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

96. 发明授权

US08198103B2 Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist 有权
标题翻译：添加压敏烃气体到由抗蚀剂掩蔽的掺杂多晶硅蚀刻
公开(公告)号：US08198103B2
公开(公告)日：2012-06-12
申请号：US12170634
申请日：2008-07-10
申请人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

97. 发明授权

US08159042B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US08159042B2
公开(公告)日：2012-04-17
申请号：US12144229
申请日：2008-06-23
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

98. 发明授权

US08009453B2 High density planar magnetic domain wall memory apparatus 有权
标题翻译：高密度平面磁畴壁存储装置
公开(公告)号：US08009453B2
公开(公告)日：2011-08-30
申请号：US12136089
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/08 , G11C19/38
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。

99. 发明授权

US07865694B2 Three-dimensional networking structure 有权
标题翻译：三维网络结构
公开(公告)号：US07865694B2
公开(公告)日：2011-01-04
申请号：US11382967
申请日：2006-05-12
申请人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
发明人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
IPC分类号： G06F15/76
CPC分类号： H01L25/0652 , H01L25/18 , H01L2225/06562 , H01L2924/0002 , H01L2924/00
摘要： A multi-layer silicon stack architecture includes one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.
摘要翻译：多层硅堆栈架构包括一个或多个包括一个或多个计算元件的处理层; 布置在处理层之间的一个或多个网络层，网络层包括一个或多个网络元件，其中每个计算元件包括到相邻布置的网络元件的多个网络连接。

100. 发明授权

US07811926B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
标题翻译：多层硬掩模方案，用于SiCOH电介质的无损双重镶嵌加工
公开(公告)号：US07811926B2
公开(公告)日：2010-10-12
申请号：US12198602
申请日：2008-08-26
申请人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： H01L21/00
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.
摘要翻译：具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

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