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91. 发明授权

US08634235B2 Phase change memory coding 有权
标题翻译：相变存储器编码
公开(公告)号：US08634235B2
公开(公告)日：2014-01-21
申请号：US12823508
申请日：2010-06-25
申请人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： Hsiang-Lan Lung , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

92. 发明申请

US20120327708A1 HIGH-ENDURANCE PHASE CHANGE MEMORY DEVICES AND METHODS FOR OPERATING THE SAME 有权
标题翻译：高耐久性相变记忆体装置及其操作方法
公开(公告)号：US20120327708A1
公开(公告)日：2012-12-27
申请号：US13472395
申请日：2012-05-15
申请人： Pei-Ying DU , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
发明人： Pei-Ying DU , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0021
摘要： Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.
摘要翻译：基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。响应于相变存储单元的置位或复位故障执行高电流修复操作。更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。

93. 发明申请

US20120170359A1 Phase Change Memory With Fast Write Characteristics 有权
标题翻译：具有快写特性的相变存储器
公开(公告)号：US20120170359A1
公开(公告)日：2012-07-05
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00 , H01L21/02
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

94. 发明授权

US08138540B2 Trench type non-volatile memory having three storage locations in one memory cell 有权
标题翻译：在一个存储单元中具有三个存储位置的沟槽型非易失性存储器
公开(公告)号：US08138540B2
公开(公告)日：2012-03-20
申请号：US11258490
申请日：2005-10-24
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory. The non-volatile memory comprises a substrate, a conductive layer, a charge storage layer, several first doped regions and several second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is located over the substrate, wherein the conductive layer fills in the trenches. The charge storage layer is located between the substrate and the conductive layer. The first doped regions are located in the substrate adjacent to both sides of the trenches respectively, wherein the first doped regions between the neighboring trenches are separated from each other. The second doped regions are located in a portion of the substrate under the bottoms of the trenches respectively.
摘要翻译：非易失性存储器。非易失性存储器包括衬底，导电层，电荷存储层，几个第一掺杂区域和几个第二掺杂区域。衬底具有形成在其中的多个沟槽。导电层位于衬底上，其中导电层填充在沟槽中。电荷存储层位于基板和导电层之间。第一掺杂区域分别位于与沟槽两侧相邻的衬底中，其中相邻沟槽之间的第一掺杂区域彼此分离。第二掺杂区域分别位于沟槽底部的衬底的一部分中。

95. 发明授权

US08072810B2 Program and erase methods with substrate transient hot carrier injections in a non-volatile memory 有权
标题翻译：在非易失性存储器中进行衬底瞬态热载体注入的编程和擦除方法
公开(公告)号：US08072810B2
公开(公告)日：2011-12-06
申请号：US12985743
申请日：2011-01-06
申请人： Tzu-Hsuan Hsu , Chao-I Wu , Kuang-Yeu Hsieh , Ya-Chin King
发明人： Tzu-Hsuan Hsu , Chao-I Wu , Kuang-Yeu Hsieh , Ya-Chin King
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.
摘要翻译：本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到电荷捕获结构。

96. 发明授权

US08036027B2 Semiconductor device and memory 有权
标题翻译：半导体器件和存储器
公开(公告)号：US08036027B2
公开(公告)日：2011-10-11
申请号：US12642272
申请日：2009-12-18
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/105 , H01L27/11568
摘要： A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively.
摘要翻译：提供了适用于嵌入式存储器的存储器。存储器包括衬底，栅极，电荷俘获栅极电介质层，源极和漏极。栅极设置在衬底上方。电荷捕获栅极电介质层设置在栅极和衬底之间。源极和漏极分别设置在栅极旁边的衬底中。

97. 发明授权

US07986558B2 Method of operating non-volatile memory cell and memory device utilizing the method 有权
标题翻译：使用该方法操作非易失性存储单元和存储器件的方法
公开(公告)号：US07986558B2
公开(公告)日：2011-07-26
申请号：US12326283
申请日：2008-12-02
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/0408 , G11C16/0466 , G11C16/107 , H01L29/78654 , H01L29/792
摘要： A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.
摘要翻译：描述了操作非易失性存储器单元的方法，包括通过双侧偏置（DSB）注入第一类型的载波来预擦除该单元，并通过第二类型的Fowler-Nordheim（FN）隧穿对该单元进行编程的载体。

98. 发明授权

US07982262B2 NAND memory device with inversion bit lines 有权
标题翻译：具有反转位线的NAND存储器件
公开(公告)号：US07982262B2
公开(公告)日：2011-07-19
申请号：US12756687
申请日：2010-04-08
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/7887
摘要： A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.
摘要翻译：基于NAND的存储器件使用反转位线以消除对注入位线的需要。结果，可以减小电池尺寸，这可以在较小包装中提供更大的密度。另一方面，公开了一种制造使用反转位线的基于NAND的存储器件的方法。

99. 发明授权

US07881112B2 Program and erase methods with substrate transient hot carrier injections in a non-volatile memory 有权
公开(公告)号：US07881112B2
公开(公告)日：2011-02-01
申请号：US12538582
申请日：2009-08-10
申请人： Tzu-Hsuan Hsu , Chao-I Wu , Kuang-Yeu Hsieh , Ya-Chin King
发明人： Tzu-Hsuan Hsu , Chao-I Wu , Kuang-Yeu Hsieh , Ya-Chin King
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

100. 发明申请

US20100193858A1 NAND MEMORY DEVICE WITH INVERSION BIT LINES AND METHODS FOR MAKING THE SAME 有权
标题翻译：具有反相位线的NAND存储器件及其制造方法
公开(公告)号：US20100193858A1
公开(公告)日：2010-08-05
申请号：US12756687
申请日：2010-04-08
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/66825 , H01L29/7887
摘要： A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.
摘要翻译：基于NAND的存储器件使用反转位线以消除对注入位线的需要。结果，可以减小电池尺寸，这可以在较小包装中提供更大的密度。另一方面，公开了一种制造使用反转位线的基于NAND的存储器件的方法。

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