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91. 发明申请

US20050280121A1 Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs 有权
标题翻译：用于高迁移率平面和多栅极MOSFET的混合衬底技术
公开(公告)号：US20050280121A1
公开(公告)日：2005-12-22
申请号：US10872605
申请日：2004-06-21
申请人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
发明人： Bruce Doris , Meikei Ieong , Edward Nowak , Min Yang
IPC分类号： H01L21/20 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L29/04 , H01L29/76
CPC分类号： H01L21/76251 , H01L21/76243 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/785
摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.
摘要翻译：提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

92. 发明申请

US20050224890A1 FinFET transistor and circuit 有权
标题翻译： FinFET晶体管和电路
公开(公告)号：US20050224890A1
公开(公告)日：2005-10-13
申请号：US10709076
申请日：2004-04-12
申请人： Kerry Bernstein , Edward Nowak , BethAnn Rainey
发明人： Kerry Bernstein , Edward Nowak , BethAnn Rainey
IPC分类号： H01L27/08 , H01L21/335 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/04 , H01L29/772 , H01L29/786
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
摘要翻译：驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有最少一个双门翅和一个分闸门。

93. 发明申请

US20050199984A1 HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 失效
标题翻译：高性能CMOS SOI器件在混合晶体导向衬底上的应用
公开(公告)号：US20050199984A1
公开(公告)日：2005-09-15
申请号：US10708586
申请日：2004-03-12
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L21/82 , H01L21/8238 , H01L27/02 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/04 , H01L29/786
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/785
摘要： Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the substrate that have a second type of crystalline orientation. The straining layer is above the first-type transistors and the second-type transistors. Further, the straining layer can be strained above the first-type transistors and relaxed above the second-type transistors.
摘要翻译：公开了具有至少两种晶体取向的基板的集成电路结构。第一类型晶体管位于具有第一类型的晶体取向的衬底的第一部分上，并且第二类型晶体管位于具有第二类型晶体取向的衬底的第二部分上。应变层位于第一型晶体管和第二型晶体管之上。此外，应变层可以应变在第一型晶体管上方并在第二型晶体管之上松弛。

94. 发明申请

US20050191346A1 Delivery capsules 审中-公开
标题翻译：送胶囊
公开(公告)号：US20050191346A1
公开(公告)日：2005-09-01
申请号：US10701293
申请日：2003-11-03
申请人： Edward Nowak , Barry Muncaster , Malcolm Brown
发明人： Edward Nowak , Barry Muncaster , Malcolm Brown
IPC分类号： A61J3/07 , A61K8/11 , A61K9/48 , A61K47/32 , A61K47/34 , A61K47/36 , A61K47/38
CPC分类号： A61J3/07 , A61K9/4808
摘要： A delivery capsule, designed to retain and protect its contents until an intended site of delivery or conditions of delivery are encountered, has at least two separate chambers (18, 20), the chambers usually containing different materials. The capsule is preferably internally divided by a dividing wall or septum (16), conveniently in the form of a median wall symmetrically arranged to form two chambers of similar size and shape. Also disclosed are a method of encapsulation and encapsulation apparatus.
摘要翻译：设计用于保持和保护其内容物直到出现预定的运送地点或运送条件的运送胶囊具有至少两个单独的腔室（18,20），该腔室通常包含不同的材料。胶囊优选由分隔壁或隔膜（16）内部分开，方便地以对称布置的中间壁的形式形成两个具有相似尺寸和形状的室。还公开了一种封装和封装装置的方法。

95. 发明申请

US20050073005A1 HIGH-DENSITY SPLIT-GATE FINFET 失效
标题翻译：高密度分离栅FINFET
公开(公告)号：US20050073005A1
公开(公告)日：2005-04-07
申请号：US10605544
申请日：2003-10-07
申请人： Edward Nowak , BethAnn Rainey
发明人： Edward Nowak , BethAnn Rainey
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795
摘要： Disclosed is a method and structure for forming a split-gate fin-type field effect transistor (FinFET). The invention produces a split-gate fin-type field effect transistor (FinFET) that has parallel fin structures. Each of the fin structures has a source region at one end, a drain region at the other end, and a channel region in the middle portion. Back gate conductors are positioned between channel regions of alternating pairs of the fin structures and front gate conductors are positioned between channel regions of opposite alternating pairs of the fin structures. Thus, the back gate conductors and the front gate conductors are alternatively inter-digitated between channel regions of the fin structures.
摘要翻译：公开了用于形成分裂栅极鳍型场效应晶体管（FinFET）的方法和结构。本发明产生具有平行翅片结构的分裂栅极鳍型场效应晶体管（FinFET）。每个翅片结构的一端具有源极区域，另一端处的漏极区域和中间部分中的沟道区域。背栅导体定位在翅片结构的交替对的通道区域之间，并且前栅极导体位于翅片结构的相对交替对的通道区域之间。因此，背栅极导体和前栅极导体在散热片结构的沟道区域之间被交替地数位化。

96. 发明申请

US20130215589A1 DEVICES FOR ACCESSORY INTEGRATION 审中-公开
标题翻译：配件集成设备
公开(公告)号：US20130215589A1
公开(公告)日：2013-08-22
申请号：US13400485
申请日：2012-02-20
申请人： Edward Nowak , Kenneth G. Seidl , Paul F. Stangl
发明人： Edward Nowak , Kenneth G. Seidl , Paul F. Stangl
IPC分类号： H05K7/02
CPC分类号： A47B21/06
摘要： The invention provides devices for integration of accessory devices, and systems employing such devices. In particular embodiments, devices described herein provide structural support for and/or electrical power to accessory devices.
摘要翻译：本发明提供了用于集成附件装置的装置以及采用这种装置的系统。在具体实施例中，本文所述的装置为附件装置提供和/或电力的结构支持。

97. 发明申请

US20080119805A1 Drainage Bag 审中-公开
标题翻译：排水袋
公开(公告)号：US20080119805A1
公开(公告)日：2008-05-22
申请号：US12013112
申请日：2008-01-11
申请人： Malcolm Brown , Louise Mulroy , Edward Nowak
发明人： Malcolm Brown , Louise Mulroy , Edward Nowak
IPC分类号： A61F5/445
CPC分类号： A61L28/0034
摘要： A drainage bag for receiving bodily waste, such as an ostomy bag, comprises an outer bag of material soluble in cold water, e.g. polyvinyl alcohol, and an inner bag of material insoluble in water at ambient temperature and body temperature but soluble in organic solvent, e.g. 2-oxepanone polymer (polycaprolactone). When the bag (and contents) are to be disposed of, appropriate organic solvent (e.g. benzyl alcohol) is applied to the inner bag. The bag can then be placed in a WC bowl and is flushable after about 1-2 minutes.
摘要翻译：用于接收身体废物的排水袋，例如造口袋，包括可溶于冷水的外部材料袋，例如，聚乙烯醇和在环境温度和体温下不溶于水的材料的内袋，但是可溶于有机溶剂，例如， 2-氧杂环戊酮聚合物（聚己内酯）。当要处理袋子（和内容物）时，将合适的有机溶剂（例如苄醇）施加到内袋上。然后将袋子放置在WC碗中，并在约1-2分钟后可冲洗。

98. 发明申请

US20080042202A1 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS 审中-公开
标题翻译： QUASI自对准源/漏极FinFET工艺
公开(公告)号：US20080042202A1
公开(公告)日：2008-02-21
申请号：US11874753
申请日：2007-10-18
申请人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
发明人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66818 , H01L29/785
摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
摘要翻译：提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。本发明还涉及利用本发明的方法形成的所得半导体结构。

99. 发明申请

US20070184594A1 SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE 有权
标题翻译：肖特基阻挡二极管和形成肖特基二极管二极管的方法
公开(公告)号：US20070184594A1
公开(公告)日：2007-08-09
申请号：US11736599
申请日：2007-04-18
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/338
CPC分类号： H01L29/872 , H01L29/66143
摘要： Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.
摘要翻译：公开了可以根据标准SOI工艺流程制造的具有低正向电压的基于硅绝缘体的肖特基势垒二极管。使用SOI晶片形成活性硅岛。该岛的一个区域被n型或p型掺杂物重掺杂，一个区域用相同的掺杂剂轻掺杂，并且在两个区域之间的结点上方的顶表面上形成隔离结构。金属硅化物区域接触形成肖特基势垒的岛的轻掺杂侧。另一个分立的金属硅化物区域接触形成与肖特基势垒（即，肖特基势垒接触）的电极的岛的重掺杂区域。两个金属硅化物区域通过隔离结构彼此隔离。与离散的金属硅化物区域中的每一个的接触允许将正向和/或反向偏压施加到肖特基势垒。

100. 发明申请

US20070102747A1 COMPLEMENTARY CARBON NANOTUBE TRIPLE GATE TECHNOLOGY 有权
标题翻译：补充碳纳米管三叶栅技术
公开(公告)号：US20070102747A1
公开(公告)日：2007-05-10
申请号：US11164109
申请日：2005-11-10
申请人： Jia Chen , Edward Nowak
发明人： Jia Chen , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L51/055 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/94
摘要： Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.
摘要翻译：公开了克服CNTFET的固有双极性能的CNT技术。本发明的一个实施例提供稳定的p型CNTFET或稳定的n型CNTFET。本发明的另一实施例提供了一种互补的CNT器件。为了克服CNTFET的双极性质，源极/漏极栅极被引入到与源极/漏极电极相对的CNT之下。这些源极/漏极栅极用于向CNT的端部施加正或负电压，以将相应的FET分别构造为n型或p型CNTFET。可以将两个相邻的CNTFET配置成互补CNT器件，其被配置为使得一个是n型CNTFET，另一个是p型CNTFET。为了独立地调节各个CNTFET的阈值电压，也可以在CNT下面，特别是在与前栅极相对的CNT的沟道区下方引入背栅。以这种方式，寄生电容和电阻最小化。

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