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    • 93. 发明申请
    • Double flip semiconductor device and method for fabrication
    • 双层半导体器件及其制造方法
    • US20080197369A1
    • 2008-08-21
    • US11708990
    • 2007-02-20
    • Max BatresJames IbbetsonNicholas W. MedendorpJulio A. Garceran
    • Max BatresJames IbbetsonNicholas W. MedendorpJulio A. Garceran
    • H01L33/00H01L21/00
    • H01L33/0079H01L33/22H01L33/405H01L33/44
    • A double flip-chip semiconductor device formed by a double flip fabrication process. Epitaxial layers are grown on a substrate in the normal fashion with the n-type layers grown first and the p-type layers grown subsequently. The chip is flipped a first time and mounted to a sacrificial layer. The original substrate is removed, exposing the n-type layer, and various additional layers and treatments are added to the device. Because the n-type layer is exposed during fabrication, the layer may be processed in various ways including adding a reflective element, texturing the surface or adding microstructures to the layer to improve light extraction. The chip is flipped a second time and mounted to a support element. The sacrificial layer is then removed and additional layers and treatment are added to the device. The finished device features a configuration in which the layers maintain the same orientation with respect to the support element that they had with the original substrate on which they were grown. Processing the n-type layers, rather than the p-type layers as in a single flip process, provides greater design flexibility when selecting features to add to the device. Thus, previously unavailable processes and reflective elements may be utilized, enhancing the external quantum efficiency of the device.
    • 通过双层翻转制造工艺形成的双倒装芯片半导体器件。 以正常方式在衬底上生长外延层,其中首先生长n型层,随后生长p型层。 芯片首次翻转并安装到牺牲层。 去除原始基底,暴露n型层,并将各种附加层和处理添加到该装置中。 因为n型层在制造过程中被曝光,所以该层可以以各种方式加工,包括添加反射元件,使表面纹理化或者向层中添加微结构以改善光提取。 芯片第二次翻转并安装在支撑元件上。 然后去除牺牲层,并向设备添加附加层和处理。 完成的装置具有这样的构造,其中层相对于它们与其生长在其上的原始基底所具有的支撑元件保持相同的取向。 在单次翻转过程中处理n型层而不是p型层,在选择要添加到设备中的特征时,提供更大的设计灵活性。 因此,可以利用先前不可用的处理和反射元件,增强器件的外部量子效率。
    • 96. 发明申请
    • Molded chip fabrication method and apparatus
    • 成型芯片制造方法和装置
    • US20050062140A1
    • 2005-03-24
    • US10666399
    • 2003-09-18
    • Michael LeungEric TarsaJames Ibbetson
    • Michael LeungEric TarsaJames Ibbetson
    • H01L21/56H01L33/50H01L23/02
    • H01L33/504H01L21/565H01L24/96H01L27/15H01L33/50H01L2224/2518H01L2924/12041H01L2924/181H01L2924/1815H01L2933/0041H01L2924/00
    • A method and apparatus for coating a plurality of semiconductor devices that is particularly adapted to coating LEDs with a coating material containing conversion particles. One method according to the invention comprises providing a mold with a formation cavity. A plurality of semiconductor devices are mounted within the mold formation cavity and a curable coating material is injected or otherwise introduced into the mold to fill the mold formation cavity and at least partially cover the semiconductor devices. The coating material is cured so that the semiconductor devices are at least partially embedded in the cured coating material. The cured coating material with the embedded semiconductor devices is removed from the formation cavity. The semiconductor devices are separated so that each is at least partially covered by a layer of the cured coating material. One embodiment of an apparatus according to the invention for coating a plurality of semiconductor devices comprises a mold housing having a formation cavity arranged to hold semiconductor devices. The formation cavity is also arranged so that a curable coating material can be injected into and fills the formation cavity to at least partially covering the semiconductor devices.
    • 一种用于涂覆多个半导体器件的方法和设备,其特别适用于涂覆含有转化颗粒的涂层材料的LED。 根据本发明的一种方法包括提供具有地层腔的模具。 多个半导体器件安装在模具形成腔内,并且可固化涂层材料被注入或以其它方式被引入到模具中以填充模具形成腔并且至少部分地覆盖半导体器件。 固化涂层材料,使得半导体器件至少部分地嵌入固化的涂层材料中。 具有嵌入式半导体器件的固化的涂层材料从形成腔中移除。 半导体器件被分离成使得每个半导体器件至少部分被固化的涂层材料层覆盖。 根据本发明的用于涂覆多个半导体器件的设备的一个实施例包括具有布置成保持半导体器件的形成空腔的模具外壳。 形成空腔也被布置成使得可固化的涂层材料可以注入并填充地层腔以至少部分地覆盖半导体器件。
    • 97. 发明授权
    • High efficiency light emitters with reduced polarization-induced charges
    • 具有降低的极化诱发电荷的高效率发光体
    • US06515313B1
    • 2003-02-04
    • US09728788
    • 2000-11-28
    • James IbbetsonBrian Thibeault
    • James IbbetsonBrian Thibeault
    • H01L3300
    • H01L33/32H01L33/16
    • Naturally occurring polarization-induced electric fields in a semiconductor light emitter with crystal layers grown along a polar direction are reduced, canceled or reversed to improve the emitter's operating efficiency and carrier confinement. This is accomplished by reducing differences in the material compositions of adjacent crystal layers, grading one or more layers to generate space charges and quasi-fields that oppose polarization-induced charges, incorporating various impurities into the semiconductor that ionize into a charge state opposite to the polarization induced charges, inverting the sequence of charged atomic layers, inverting the growth sequence of n- and p-type layers in the device, employing a multilayer emission system instead of a uniform active region and/or changing the in-plane lattice constant of the material.
    • 在极性方向生长的晶体层的半导体光发射体中自然发生的极化感应电场被减少,抵消或反转,以提高发射体的工作效率和载流子限制。 这是通过减少相邻晶体层的材料组成的差异,对一个或多个层进行分级以产生空间电荷和与偏振电荷相反的准场,将各种杂质并入半导体中,将其电离成与 偏振感应电荷,反转带电原子层的序列,反转器件中n型和p型层的生长顺序,采用多层发射系统代替均匀的有源区和/或改变面内晶格常数 材料。