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    • 91. 发明申请
    • Chimeric immunoreceptor useful in treating human cancers
    • 嵌合免疫受体可用于治疗人类癌症
    • US20090257994A1
    • 2009-10-15
    • US12314195
    • 2008-12-05
    • Michael Jensen
    • Michael Jensen
    • A61K45/00C07K14/00C12N15/74A61P35/00
    • A61K38/2086A61K35/17A61K38/1774C07H21/04C07K14/5437C07K14/7051C07K14/70514C07K14/7155C07K16/46C07K19/00C07K2319/00C07K2319/30C12N5/0636C12N15/63
    • The present invention relates to chimeric transmembrane immunoreceptors, named “zetakines,” comprised of an extracellular domain comprising a soluble receptor ligand linked to a support region capable of tethering the extracellular domain to a cell surface, a transmembrane region and an intracellular signalling domain. Zetakines, when expressed on the surface of T lymphocytes, direct T cell activity to those specific cells expressing a receptor for which the soluble receptor ligand is specific. Zetakine chimeric immunoreceptors represent a novel extension of antibody-based immunoreceptors for redirecting the antigen specificity of T cells, with application to treatment of a variety of cancers, particularly via the autocrin/paracrine cytokine systems utilized by human malignancy. In a preferred embodiment is a glioma-specific immunoreceptor comprising the extracellular targetting domain of the IL-13Rα2-specific IL-13 mutant IL-13(E13Y) linked to the Fc region of IgG, the transmembrane domain of human CD4, and the human CD3 zeta chain.
    • 本发明涉及由跨膜结构域组成的嵌合跨膜免疫受体,其包含与能够将细胞外结构域连接至细胞表面的支持区连接的可溶性受体配体,跨膜区和细胞内信号结构域。 当在T淋巴细胞表面上表达时,Zetakines将T细胞活性直接导向表达可溶性受体配体特异性受体的那些特异性细胞。 Zetakine嵌合免疫受体代表了用于重定向T细胞的抗原特异性的基于抗体的免疫受体的新的延伸,其应用于治疗多种癌症,特别是通过人类恶性肿瘤使用的自身免疫/旁分泌细胞因子系统。 在一个优选的实施方案中是包含与IgG的Fc区连接的IL-13Ralpha2特异性IL-13突变体IL-13(E13Y)的细胞外靶向结构域的人胶质瘤特异性免疫受体,人CD4的跨膜结构域和人 CD3ζ链。
    • 92. 发明申请
    • Methods of synthesizing chemically cleavable phosphoramidite linkers
    • 化学可裂解亚磷酰胺接头的合成方法
    • US20090048436A1
    • 2009-02-19
    • US11893614
    • 2007-08-15
    • Keith AndersonMichael JensenRonald W. DavisCharles K. BrushKaizhang He
    • Keith AndersonMichael JensenRonald W. DavisCharles K. BrushKaizhang He
    • C07H21/00
    • C07H21/00
    • The present invention provides a method of synthesizing phosphoramidite linkers that are useful for the production of synthesizing two or more oligonucleotides in tandem. The inventive linker has the following desirable properties: (i) enhanced stability to alkali conditions versus the linkers previously published, (ii) cleaves to produce 5′ and 3′ ends that are fully biologically compatible, (iii) cleaves completely under conditions that are already used in cleavage/deprotection processes so it is fully compatible with conditions that are common in laboratories and does not require additives that necessitate further purification after cleavage, (iv) integrates easily onto commercially available synthesizers because it is compatible with standard coupling chemistry, and (v) is compatible with DNA, RNA, forward, reverse, and LNA, synthesis chemistries. In addition, the inventive linkers may be coupled to a solid support. Thus, the inventive linkers provide a significant advancement in the state of the art.
    • 本发明提供了一种合成亚磷酰胺接头的方法,其可用于串联合成两种或多种寡核苷酸。 本发明的接头具有以下所需的性质:(i)与先前公开的接头相比,提高了对碱性条件的稳定性,(ii)切割产生完全生物相容的5'和3'末端,(iii)在条件下完全切割 已经用于裂解/去保护过程,因此它与实验室常见的条件完全相容,并且不需要在裂解后需要进一步纯化的添加剂,(iv)容易地与市售合成仪整合,因为它与标准偶联化学相容,并且 (v)与DNA,RNA,正向,反向和LNA的合成化学物质相容。 此外,本发明的接头可以连接到固体支持物。 因此,本发明的接头提供了现有技术的显着进步。
    • 97. 发明申请
    • INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR
    • 用于系统寄存器位设置和清除的指令编码
    • US20070234020A1
    • 2007-10-04
    • US11567290
    • 2006-12-06
    • Michael Jensen
    • Michael Jensen
    • G06F9/48
    • G06F9/462G06F9/30018G06F9/3004G06F9/30101G06F9/30185G06F9/4812
    • An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.
    • 为微处理器提供指令编码架构,以允许对特权架构寄存器进行原子修改。 指令包括指定给微处理器的操作码,指令仅在特权(内核)状态下执行,并且指令将与特权控制寄存器进行通信,该字段用于指定多个特权体系结构寄存器中的哪一个到 被修改,用于指定要修改指定的特权体系结构寄存器中的哪些位字段的字段以及用于指定是否要设置或清除指定位字段的字段。 指令编码允许单个指令在特权体系结构寄存器中原子地设置或清除位字段,而不将特权体系结构寄存器读入通用寄存器。 此外,指令编码允许程序员指定在原子修改期间是否将特权架构寄存器的先前内容保存到通用寄存器。
    • 100. 发明申请
    • Boundary address registers for selection of ISA mode
    • 用于选择ISA模式的边界地址寄存器
    • US20070094482A1
    • 2007-04-26
    • US11636462
    • 2006-12-11
    • Michael JensenMorten Stribaek
    • Michael JensenMorten Stribaek
    • G06F9/40
    • G06F9/44547G06F9/30076G06F9/30189G06F9/30196G06F9/3802
    • An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers. The ISA mode selection logic receives the particular address, and compares it against the plurality of address ranges to determine the particular ISA decoding mode for the particular program instruction.
    • 提供了一种装置和方法,其使多个指令集体系结构(ISA)中央处理单元(CPU)在执行多个ISA应用程序期间区分与不同ISA相对应的不同程序指令。 该装置允许多ISA CPU选择与程序指令相对应的特定ISA解码模式。 程序指令位于多ISA CPU的地址空间内的地址。 该装置包括多个边界地址寄存器和ISA模式选择逻辑。 可以动态地加载多个边界地址寄存器以将地址空间分割成多个地址范围,其中多个地址范围中的每一个对应于多个ISA解码模式中的每一个。 ISA模式选择逻辑耦合到多个边界地址寄存器。 ISA模式选择逻辑接收特定地址,并将其与多个地址范围进行比较,以确定特定程序指令的特定ISA解码模式。