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91. 发明授权

US07730463B2 Efficient generation of SIMD code in presence of multi-threading and other false sharing conditions and in machines having memory protection support 有权
标题翻译：在存在多线程和其他虚假共享条件的情况下以及具有存储器保护支持的机器中有效地生成SIMD代码
公开(公告)号：US07730463B2
公开(公告)日：2010-06-01
申请号：US11358372
申请日：2006-02-21
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
IPC分类号： G06F9/45
CPC分类号： G06F9/3851 , G06F8/44
摘要： A computer implemented method, system and computer program product for automatically generating SIMD code. The method begins by analyzing data to be accessed by a targeted loop including at least one statement, where each statement has at least one memory reference, to determine if memory accesses are safe. If memory accesses are safe, the targeted loop is simdized. If not safe, it is determined if a scheme can be applied in which safety need not be guaranteed. If such a scheme can be applied, the targeted loop is simdized according to the scheme. If such a scheme cannot be applied, it is determined if padding is appropriate. If padding is appropriate, the data is padded and the targeted loop is simdized. If padding is not appropriate, non-simdized code is generated based on the targeted loop for handling boundary conditions, the targeted loop is simdized and combined with the non-simdized code.
摘要翻译：一种用于自动生成SIMD代码的计算机实现的方法，系统和计算机程序产品。该方法开始于分析要由目标循环访问的数据，包括至少一个语句，其中每个语句具有至少一个存储器引用，以确定存储器访问是否安全。如果存储器访问是安全的，则对象循环被简化。如果不安全，则确定是否可以应用不需要保证安全性的方案。如果可以应用这种方案，则根据该方案对目标循环进行模拟。如果不能应用这种方案，则确定填充是否合适。如果填充是合适的，则填充数据并对目标循环进行模拟。如果填充不合适，则基于用于处理边界条件的目标循环生成非模拟代码，目标循环被简化并与非模拟代码组合。

92. 发明申请

US20100011339A1 SINGLE INSTRUCTION MULTIPLE DATA (SIMD) CODE GENERATION FOR PARALLEL LOOPS USING VERSIONING AND SCHEDULING 失效
标题翻译：单一指令多项数据（SIMD）使用版本和调度的平行代码生成代码
公开(公告)号：US20100011339A1
公开(公告)日：2010-01-14
申请号：US12172199
申请日：2008-07-11
申请人： Alexandre E. Eichenberger , Raul E. Silvera , Amy K. Wang , Guansong Zhang
发明人： Alexandre E. Eichenberger , Raul E. Silvera , Amy K. Wang , Guansong Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/456
摘要： Embodiments of the present invention address deficiencies of the art in respect to loop parallelization for a target architecture implementing a shared memory model and provide a novel and non-obvious method, system and computer program product for SIMD code generation for parallel loops using versioning and scheduling. In an embodiment of the invention, within a code compilation data processing system a parallel SIMD loop code generation method can include identifying a loop in a representation of source code as a parallel loop candidate, either through a user directive or through auto-parallelization. The method also can include selecting a trip count condition responsive to a scheduling policy set for the code compilation data processing system and also on a minimal simdizable threshold, determining a trip count and an alignment constraint for the selected loop, and generating a version of a parallel loop in the source code according to the alignment constraint and a comparison of the trip count to the trip count condition.
摘要翻译：本发明的实施例解决了实现共享存储器模型的目标架构的环路并行化方面的技术缺陷，并且提供了一种用于使用版本控制和调度的并行循环的SIMD代码生成的新颖且非显而易见的方法，系统和计算机程序产品。在本发明的一个实施例中，在代码编译数据处理系统中，并行SIMD循环码生成方法可以包括通过用户指令或通过自动并行化来将源代码表示中的循环识别为并行循环候选。该方法还可以包括响应于针对代码编译数据处理系统的调度策略集以及最小可仿真阈值来选择跳闸计数条件，确定所选循环的跳闸计数和对准约束，以及生成根据对齐约束在源代码中并行循环，并将行程计数与行程计数条件进行比较。

93. 发明申请

US20090307673A1 System and Method for Domain Stretching for an Advanced Dual-Representation Polyhedral Loop Transformation Framework 失效
标题翻译：用于高级双表示多面体环转换框架的域拉伸的系统和方法
公开(公告)号：US20090307673A1
公开(公告)日：2009-12-10
申请号：US11861503
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/45
CPC分类号： G06F8/452
摘要： A system and method for domain stretching for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for stretching the domains of statements in a program loop view of the source code to thereby normalize the domains.
摘要翻译：提供了一种用于高级双重表示多面体环转换框架的域拉伸的系统和方法。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。另外，提供了用于在源代码的程序循环视图中拉伸语句的域的机制，从而使域标准化。

94. 发明授权

US07475392B2 SIMD code generation for loops with mixed data lengths 失效
标题翻译：具有混合数据长度的循环的SIMD代码生成
公开(公告)号：US07475392B2
公开(公告)日：2009-01-06
申请号：US10919131
申请日：2004-08-16
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452
摘要： Generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths, is disclosed. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime alignment. Length conversion operations, for packing and unpacking data values, are included in the alignment handling framework. These operations are formally defined in terms of standard SIMD instructions that are readily available on various SIMD platforms. This allows sequential loop code operating on datatypes of disparate length to be transformed (“simdized”) into optimized SIMD code through a fully automated process.
摘要翻译：公开了在单指令多数据路径（SIMD）架构中生成循环码，其循环对具有不同长度的数据类型进行操作。此外，本发明的优选实施例包括一种用于有效地将任意流重新对准或将任意流移动到任意偏移的新技术，无论在编译时是否知道对准或偏移。这种技术使得可以将高级对齐优化应用于运行时对齐。用于打包和解包数据值的长度转换操作包含在对齐处理框架中。这些操作根据在各种SIMD平台上容易获得的标准SIMD指令正式定义。这允许对具有不同长度的数据类型的顺序循环代码通过完全自动化的过程进行转换（“模拟化”）成优化的SIMD代码。

95. 发明申请

US20080127144A1 METHOD TO EXPLOIT SUPERWORD-LEVEL PARALLELISM USING SEMI-ISOMORPHIC PACKING 失效
标题翻译：使用半正交包装开发超级平行平行的方法
公开(公告)号：US20080127144A1
公开(公告)日：2008-05-29
申请号：US11536990
申请日：2006-09-29
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A computer program product is provided for extracting SIMD parallelism. The computer program product includes instructions for providing a stream of input code comprising basic blocks; identifying pairs of statements that are semi-isomorphic with respect to each other within a basic block; iteratively combining into packs, pairs of statements that are semi-isomorphic with respect to each other, and combining packs into combined packs; collecting packs whose statements can be scheduled together for processing; and generating SIMD instructions for each pack to provide for extracting the SIMD parallelism.
摘要翻译：提供了一种用于提取SIMD并行性的计算机程序产品。计算机程序产品包括用于提供包括基本块的输入代码流的指令; 识别在基本块内相对于彼此半同构的语句对; 迭代地组合成包，相对于半同构的语句对，以及将包合并成组合包; 收集包，其陈述可以一起安排处理; 并为每个包生成SIMD指令以提供SIMD并行性。

96. 发明申请

US20080065809A1 OPTIMIZED SOFTWARE CACHE LOOKUP FOR SIMD ARCHITECTURES 有权
标题翻译：优化的软件高速缓存用于SIMD架构
公开(公告)号：US20080065809A1
公开(公告)日：2008-03-13
申请号：US11470638
申请日：2006-09-07
申请人： Alexandre E. Eichenberger
发明人： Alexandre E. Eichenberger
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a cache directory using a Single Instruction Multiple Data (SIMD) operation, determining a position of the requested address in the set using a SIMD comparison, and determining an actual data value associated with the position of the requested address in the set.
摘要翻译：处理，高速缓冲存储器，计算机产品和系统，用于在软件缓存中加载与所请求的地址相关联的数据。该过程包括使用单指令多数据（SIMD）操作将与集合相关联的地址标签加载到高速缓存目录中，使用SIMD比较确定所述集合中的请求地址的位置，以及确定与该位置相关联的实际数据值的集合中的请求地址。

97. 发明授权

US08577950B2 Matrix multiplication operations with data pre-conditioning in a high performance computing architecture 失效
标题翻译：在高性能计算架构中使用数据预处理的矩阵乘法运算
公开(公告)号：US08577950B2
公开(公告)日：2013-11-05
申请号：US12542255
申请日：2009-08-17
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F7/52
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/30094 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
摘要翻译：提供了用于在高性能计算架构中执行数据预处理的矩阵乘法运算的机制。执行向量加载操作以将矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。执行加载和拼接操作以加载第二向量操作数的元素并将元素复制到第二目标向量寄存器的多个元素中的每一个。对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行乘法加法运算，以生成矩阵乘法运算的部分乘积。矩阵乘法运算的部分乘积与矩阵乘法运算的其他部分积积累。

98. 发明授权

US08572359B2 Runtime extraction of data parallelism 有权
标题翻译：运行时提取数据并行性
公开(公告)号：US08572359B2
公开(公告)日：2013-10-29
申请号：US12649860
申请日：2009-12-30
申请人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
发明人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F8/4441 , G06F9/381 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3859
摘要： Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.
摘要翻译：提供了在运行时提取数据依赖关系的机制。所述机制执行具有循环的一部分代码，并为所述循环生成包括小于所述循环的总迭代次数的循环迭代子集的第一并行执行组。机制进一步执行第一个并行执行组，并确定迭代子集中的每个迭代，迭代是否具有数据依赖性。此外，机制仅将数据存储到系统存储器中，用于仅在确定了数据依赖性的迭代子集中通过迭代执行的存储。在确定数据相关性的迭代子集中存储由迭代执行的存储数据不会提交给系统存储器。

99. 发明授权

US08561043B2 Data transfer optimized software cache for irregular memory references 有权
标题翻译：数据传输优化的软件缓存用于不规则内存引用
公开(公告)号：US08561043B2
公开(公告)日：2013-10-15
申请号：US12057456
申请日：2008-03-28
申请人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45 , G06F12/08
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for optimizing irregular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which irregular memory references access a storage of a software cache of a data processing system through a transactional cache mechanism of the software cache.
摘要翻译：提供机制用于优化计算机代码中的不规则内存引用。这些机制可能解析计算机代码以识别计算机代码中的内存引用。这些机制可以将计算机代码中的存储器引用进一步分类为常规存储器引用或不规则存储器引用。此外，机制可以通过编译器转换计算机代码，以生成转换的计算机代码，其中不规则存储器引用通过软件高速缓存的事务高速缓存机制访问数据处理系统的软件高速缓存的存储。

100. 发明授权

US08468539B2 Tracking and detecting thread dependencies using speculative versioning cache 有权
标题翻译：使用推测版本缓存来跟踪和检测线程依赖关系
公开(公告)号：US08468539B2
公开(公告)日：2013-06-18
申请号：US12553314
申请日：2009-09-03
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
IPC分类号： G06F9/46
CPC分类号： G06F9/3814 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3859
摘要： Mechanisms are provided for tracking dependencies of threads in a multi-threaded computer program execution. The mechanisms detect a dependency of a first thread's execution on results of a second thread's execution in an execution flow of the multi-threaded computer program. The mechanisms further store, in a hardware thread dependency vector storage associated with the first thread's execution, an identifier of the dependency by setting at least one bit in the hardware thread dependency vector storage corresponding to the second thread. Moreover, the mechanisms schedule tasks performed by the multi-threaded computer program based on the hardware thread dependency vector storage to minimize squashing of threads.
摘要翻译：提供了用于跟踪多线程计算机程序执行中线程依赖性的机制。该机制检测第一个线程执行对多线程计算机程序执行流程中第二个线程执行结果的依赖性。这些机制通过在与第二线程相对应的硬件线程相关性向量存储中设置至少一个比特来进一步存储与第一线程的执行相关联的硬件线程依赖向量存储中的依赖关系的标识符。此外，该机制基于硬件线程依赖向量存储来调度由多线程计算机程序执行的任务以最小化线程的挤压。

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