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91. 发明授权

US06981163B2 Method and apparatus for power mode transition in a multi-thread processor 失效
标题翻译：多线程处理器中功率模式转换的方法和装置
公开(公告)号：US06981163B2
公开(公告)日：2005-12-27
申请号：US10887488
申请日：2004-07-07
申请人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
发明人： Bret L. Toll , Alan B. Kyker , Stephen H. Gunther
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/329 , Y02D10/128 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.
摘要翻译：一种用于多线程处理器中功率模式转换的方法和装置。发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

92. 发明授权

US5860106A Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 失效
标题翻译：用于动态调整存储器子系统的功率/性能特性的方法和装置
公开(公告)号：US5860106A
公开(公告)日：1999-01-12
申请号：US502094
申请日：1995-07-13
申请人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
发明人： Stanley J. Domen , Dileep R. Idate , Stephen H. Gunther , George Thangadurai
IPC分类号： G06F12/02 , G06F12/08 , G11C11/413 , G06F9/38 , G06F1/32
CPC分类号： G11C11/413 , G06F12/0215 , G06F12/0802 , G06F2212/1028 , Y02B60/1225
摘要： An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
摘要翻译：一种用于动态调整存储器子系统的功率/性能特性的装置和方法。由于存储器子系统访问要求在很大程度上取决于正在执行的应用程序，所以启用或禁用各个存储器系统组件（如现有技术中所使用的）的静态方法从功耗角度来看不是最佳的。通过动态跟踪存储器子系统的行为，本发明预测下一个事件将具有某些特征的概率，例如它是否会导致需要高速缓冲存储器注意的存储器周期，该存储器周期是否会导致高速缓冲存储器命中，以及如果请求的数据不在高速缓冲存储器的一个级别中，是否将在主存储器中命中DRAM页面。基于这些概率，本发明动态地启用或禁用子系统的组件。通过智能地调整这些组件的状态，可以实现显着的功率节省，而不会降低性能。

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