专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20140136745A1 METHOD AND APPARATUS FOR ALLOCATING INTERRUPTS IN A MULTI-CORE SYSTEM 审中-公开
标题翻译：用于在多核系统中分配中断的方法和装置
公开(公告)号：US20140136745A1
公开(公告)日：2014-05-15
申请号：US14234265
申请日：2012-08-10
申请人： Sang Bok Han , Hong Chul Kim , In Choon Yeo , Jong-Chul Park
发明人： Sang Bok Han , Hong Chul Kim , In Choon Yeo , Jong-Chul Park
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An apparatus and a method for allocating interrupts in a multi-core system are provided. According to an embodiment, an interrupt control register unit records the interrupt processing capacity of each core of a multi-core system by receiving an interrupt, and checking the interrupt control register unit when receiving the interrupt and allocating the interrupt to a core which has been checked to be in an interrupt processing enabled state in the checking step. When the core is allocating the interrupt, the core transmits, to the interrupt control register unit, a signal representing the interrupt control register corresponding to the core which is changed to an interrupt processing disabled state, and can process the interrupt.
摘要翻译：提供了一种用于在多核系统中分配中断的装置和方法。根据实施例，中断控制寄存器单元通过接收中断来记录多核系统的每个核的中断处理能力，并且在接收到中断时检查中断控制寄存器单元，并将中断分配给已经被检查在检查步骤中处于启用中断状态。当核心分配中断时，核心向中断控制寄存器单元发送一个表示与核心相对应的中断控制寄存器的信号，该中断控制寄存器改变为中断处理禁止状态，并且可以处理中断。

92. 发明授权

US08551888B2 Method of forming patterns for semiconductor device 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US08551888B2
公开(公告)日：2013-10-08
申请号：US13238945
申请日：2011-09-21
申请人： Yun-seung Kang , Jong-chul Park , Kwang-yong Yang , Sang-sup Jeong , Seok-hyun Lim
发明人： Yun-seung Kang , Jong-chul Park , Kwang-yong Yang , Sang-sup Jeong , Seok-hyun Lim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/32139 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.
摘要翻译：一种形成半导体器件的图案的方法。该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

93. 发明申请

US20120129349A1 METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案的方法
公开(公告)号：US20120129349A1
公开(公告)日：2012-05-24
申请号：US13238945
申请日：2011-09-21
申请人： Yun-seung Kang , Jong-chul Park , Kwang-yong Yang , Sang-sup Jeong , Seok-hyun Lim
发明人： Yun-seung Kang , Jong-chul Park , Kwang-yong Yang , Sang-sup Jeong , Seok-hyun Lim
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/32139 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： A method of forming patterns for a semiconductor device. The method includes: forming a first hard mask layer on a layer which is to be etched; forming a second hard mask layer on the first hard mask layer, wherein the second hard mask layer includes a first portion and a second portion formed underneath the first portion, wherein the first portion and second portion are composed of the same material; etching the first portion to form first patterns; forming spacers covering sidewalls of the first patterns; etching the second portion using the spacers as etch masks to form second patterns; etching the first hard mask layer and the spacers using the second patterns disposed underneath the spacers as etch masks to form third patterns; and etching the layer to be etched, using the third patterns.
摘要翻译：一种形成半导体器件的图案的方法。该方法包括：在要蚀刻的层上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层，其中所述第二硬掩模层包括形成在所述第一部分下面的第一部分和第二部分，其中所述第一部分和第二部分由相同的材料构成; 蚀刻第一部分以形成第一图案; 形成覆盖所述第一图案的侧壁的间隔物; 使用间隔物蚀刻第二部分作为蚀刻掩模以形成第二图案; 使用设置在间隔物下方的第二图案作为蚀刻掩模来蚀刻第一硬掩模层和间隔物以形成第三图案; 并使用第三图案蚀刻待蚀刻的层。

94. 发明授权

US08111559B2 Non-volatile random access memory with a control circuit for preventing an initial resistance failure, a solid state drive, and a computer system including the same 有权
标题翻译：具有用于防止初始电阻故障的控制电路的非易失性随机存取存储器，固态驱动器和包括其的计算机系统
公开(公告)号：US08111559B2
公开(公告)日：2012-02-07
申请号：US12662221
申请日：2010-04-06
申请人： Min Cheol Kwon , Dong Jun Shin , Sun-Mi Yoo , Jong-Chul Park
发明人： Min Cheol Kwon , Dong Jun Shin , Sun-Mi Yoo , Jong-Chul Park
IPC分类号： G11C7/10
CPC分类号： G11C7/04 , G06F3/0679 , G11C7/22 , G11C13/004 , G11C13/0069
摘要： The non-volatile random access memory (RAM) includes a non-volatile RAM array, a buffer configured to buffer data to be programmed in the non-volatile RAM array and configured to buffer data read from the non-volatile RAM array, and a control block configured to read data from at least one of the non-volatile RAM array and the buffer based on whether the data to be read has been stored in the buffer, a temperature when the data was programmed, and a time lapse since the programming of the data.
摘要翻译：非易失性随机存取存储器（RAM）包括非易失性RAM阵列，被配置为缓冲要在非易失性RAM阵列中编程的数据并被配置为缓冲从非易失性RAM阵列读取的数据的缓冲器，以及控制块，其被配置为基于是否将要读取的数据存储在缓冲器中，从数据被编程的温度以及从编程开始的时间流逝从非易失性RAM阵列和缓冲器中的至少一个读取数据的数据。

95. 发明授权

US08053358B2 Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation 有权
公开(公告)号：US08053358B2
公开(公告)日：2011-11-08
申请号：US12965091
申请日：2010-12-10
申请人： Doo-young Lee , Sang-sup Jeong , Sung-gil Choi , Jong-chul Park , Jin-young Kim , Ki-jin Park
发明人： Doo-young Lee , Sang-sup Jeong , Sung-gil Choi , Jong-chul Park , Jin-young Kim , Ki-jin Park
IPC分类号： H01L23/58
CPC分类号： H01L21/76897 , H01L21/76831
摘要： Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

96. 发明授权

US07980838B2 Electric spinning apparatus for mass-production of nano-fiber 有权
标题翻译：用于大规模生产纳米纤维的电纺丝设备
公开(公告)号：US07980838B2
公开(公告)日：2011-07-19
申请号：US12078003
申请日：2008-03-26
申请人： Jong-Chul Park
发明人： Jong-Chul Park
IPC分类号： D01D5/00 , D04H3/03
CPC分类号： D01D5/0069 , B82Y30/00
摘要： The present invention relates to an electrospinning apparatus for mass-production of nanofibers, particularly to an electrospinning apparatus with an electric stability and an improved nozzle blocks. The bottom-up electrospinning apparatus for the mass-production of nanofiber comprises at least one nozzle block having a plurality of spinning nozzles arranged in the horizontal and vertical direction; a collector installed over the nozzle blocks in order to correspond to the nozzle blocks and maintain a certain distance in between; a power source to apply voltage difference between the nozzle block and the collector; and a spinning solution container to supply the spinning solution to the nozzle block, wherein the nozzle block and the collector are connected to the positive terminal and the negative terminal, respectively and among a plurality of spinning nozzles arranged along the horizontal line, a spinning nozzle in the middle and a spinning nozzle in the end have different height.
摘要翻译：本发明涉及一种用于批量生产纳米纤维的静电纺丝装置，特别涉及具有电稳定性和改进的喷嘴块的静电纺丝装置。用于批量生产纳米纤维的自下而上的静电纺丝装置包括至少一个具有在水平和垂直方向上布置的多个纺丝喷嘴的喷嘴块; 安装在喷嘴块上的收集器，以便对应于喷嘴块并在其间保持一定的距离; 用于施加喷嘴块和收集器之间的电压差的电源; 以及将纺丝溶液供给到喷嘴块的纺丝溶液容器，其中喷嘴块和集电器分别连接到正极端子和负极端子，并且沿着水平线布置的多个纺丝喷嘴中，纺丝喷嘴在中间和纺纱喷嘴的末端有不同的高度。

97. 发明申请

US20100216289A1 Method of fabricating semiconductor device having metal-semiconductor compound regions 有权
标题翻译：制造具有金属 - 半导体化合物区域的半导体器件的方法
公开(公告)号：US20100216289A1
公开(公告)日：2010-08-26
申请号：US12656885
申请日：2010-02-18
申请人： Jong-Chul Park , Yun-Seung Kang
发明人： Jong-Chul Park , Yun-Seung Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/456 , H01L29/66666
摘要： Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.
摘要翻译：示例性实施例涉及制造具有金属 - 半导体化合物区域的半导体器件的方法。根据示例性实施例的方法可以包括在半导体衬底上形成半导体柱。半导体柱之间的半导体衬底可以被蚀刻以形成沟槽区域。可以形成部分地填充沟槽区域的介电隔离图案，并且可以在半导体柱的侧壁上形成电介质侧壁间隔物。金属 - 半导体化合物区域可以形成在未被隔离图案填充的沟槽区域的一部分的侧壁上。

98. 发明申请

US20100169806A1 Apparatus and method for creating widget in portable terminal 有权
标题翻译：便携式终端中创建小部件的装置和方法
公开(公告)号：US20100169806A1
公开(公告)日：2010-07-01
申请号：US12655381
申请日：2009-12-30
申请人： Jeong-Hoe Ku , Jong-Chul Park , Ji-Won Ha
发明人： Jeong-Hoe Ku , Jong-Chul Park , Ji-Won Ha
IPC分类号： G06F3/048 , G06F9/54
CPC分类号： G06F8/38
摘要： Provided are an apparatus and a method for creating a widget of a portable terminal. The method includes: determining a building block that a user selects on a widget creating screen including building blocks necessary for widget creation; generating a tag of data corresponding to the confirmed building block; and generating a widget code including the building block and the tag.
摘要翻译：提供了一种用于创建便携式终端的小部件的装置和方法。该方法包括：确定用户在小窗口创建屏幕上选择的构建块，其包括小部件创建所必需的构建块; 产生与所确认的构建块对应的数据标签; 以及生成包括所述构建块和所述标签的小部件代码。

99. 发明申请

US20090206399A1 METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR 审中-公开
标题翻译：形成记忆通道图案的方法和制作记录道信道
公开(公告)号：US20090206399A1
公开(公告)日：2009-08-20
申请号：US12430831
申请日：2009-04-27
申请人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
发明人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

100. 发明申请

US20080290507A1 CHIP EMBEDDED PRINTED CIRCUIT BOARD AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：芯片嵌入式印刷电路板及其制作方法
公开(公告)号：US20080290507A1
公开(公告)日：2008-11-27
申请号：US11947574
申请日：2007-11-29
申请人： Se Hoon Park , Jun Chul Kim , Jong Chul Park , Nam Kee Kang , Woo Sung Lee , Chan Sei Yoo
发明人： Se Hoon Park , Jun Chul Kim , Jong Chul Park , Nam Kee Kang , Woo Sung Lee , Chan Sei Yoo
IPC分类号： H01L23/36 , H01L21/58
CPC分类号： H05K1/187 , H01L2224/16 , H01L2224/82039 , H01L2224/82047 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/0203 , H05K1/0206 , H05K1/162 , H05K1/186 , H05K3/0061 , H05K3/1291 , H05K3/205 , H05K3/207 , H05K3/3436 , H05K3/4652 , H05K2201/0355 , H05K2201/09563 , H05K2201/10674 , H05K2203/0315 , H05K2203/0376 , H05K2203/0733 , H05K2203/1126 , H01L2224/0401
摘要： The chip embedded printed circuit board and a fabricating method thereof are disclosed, wherein a circuit pattern is formed by depositing a metal layer on a support layer, a semiconductor chip is packaged on a support layer to wrap the semiconductor chip and the circuit pattern on the support layer and to form an isolation layer, a via hole filled with conductive material is formed through the isolation layer for interlayer electrical connection, part of the support layer is selectively removed to form a plated heat sink, such that a packaging process can be performed in a very planar state and the plated heat sink can be integrated with a printed circuit board.
摘要翻译：公开了芯片嵌入式印刷电路板及其制造方法，其中通过在支撑层上沉积金属层形成电路图案，将半导体芯片封装在支撑层上以将半导体芯片和电路图案包裹在支撑层并形成隔离层，通过用于层间电连接的隔离层形成填充有导电材料的通孔，部分支撑层被选择性地去除以形成电镀散热器，从而可以执行封装处理在非常平坦的状态下，电镀散热器可与印刷电路板集成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式