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91. 发明申请

US20100205407A1 PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION 有权
标题翻译：具有快速非选择性正确条件分支指令解决方案的管道微处理器
公开(公告)号：US20100205407A1
公开(公告)日：2010-08-12
申请号：US12481511
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30058 , G06F9/3802 , G06F9/3867
摘要： A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a prediction of conditional branch instructions of the first type and flushes the pipeline of instructions if the prediction is subsequently determined to be incorrect, thereby incurring a branch misprediction penalty related to processing of conditional branch instructions of the first type. The microprocessor always correctly resolves conditional branch instructions of the second type without making a prediction of conditional branch instructions of the second type, thereby avoiding ever incurring a branch misprediction penalty related to processing of conditional branch instructions of the second type.
摘要翻译：微处理器包括用于处理指令的级的流水线，以及可由程序包含的第一和第二类型的条件分支指令。如果预测随后被确定为不正确，则微处理器对第一类型的条件转移指令进行预测并刷新指令的流水线，由此产生与第一类型的条件转移指令的处理相关的分支误预算罚款。微处理器总是正确地解析第二类型的条件转移指令，而不进行第二类型的条件转移指令的预测，从而避免与第二类型的条件转移指令的处理有关的分支误预算罚款。

92. 发明申请

US20100205403A1 PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC EXCEPTION STATE 有权
标题翻译：基于静态异常状态的快速条件分支指令的管道微处理器
公开(公告)号：US20100205403A1
公开(公告)日：2010-08-12
申请号：US12481427
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes the exception condition. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the exception handler. The execution unit also saves a state in response to detecting the exception condition caused by the user program instruction. A second fetch unit fetches the exception handler instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.
摘要翻译：微处理器包括存储异常处理程序来处理异常情况的存储器。异常处理程序是微处理器专用的非用户程序，并包括条件转移指令。第一提取单元获取包括导致异常条件的用户程序指令的用户程序的指令。执行单元执行由第一取出单元取出的用户程序指令，并执行异常处理程序的指令。执行单元还响应于检测到由用户程序指令引起的异常状况而保存状态。第二提取单元从存储器中取出异常处理程序指令，并且基于保存的状态解析条件转移指令，而不向执行单元发送条件转移指令来解析条件转移指令。

93. 发明申请

US20100205402A1 PIPELINED MICROPROCESSOR WITH NORMAL AND FAST CONDITIONAL BRANCH INSTRUCTIONS 有权
标题翻译：具有正常和快速条件分支指令的管道微处理器
公开(公告)号：US20100205402A1
公开(公告)日：2010-08-12
申请号：US12481118
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state.
摘要翻译：微处理器包括第一分支状态和第二分支状态。微处理器还包括第一类型的条件转移指令，指示微处理器基于第一转移条件状态等待正确地解析第一类型的条件转移指令，直到微处理器内的其他指令更新第一分支状态和比第一类型的条件分支指令更旧的第一分支条件状态。第二类型的条件分支指令指示微处理器基于第二分支条件状态来正确地解析第二类型的条件分支指令，而不考虑微处理器内是否更新第二分支条件状态并且比第二分支状态更新的其它指令第二类型的条件分支指令还更新了第二分支条件状态。

94. 发明申请

US20100011198A1 MICROPROCESSOR WITH MULTIPLE OPERATING MODES DYNAMICALLY CONFIGURABLE BY A DEVICE DRIVER BASED ON CURRENTLY RUNNING APPLICATIONS 有权
标题翻译：基于当前运行应用的设备驱动程序动态配置的多种操作模式的微处理器
公开(公告)号：US20100011198A1
公开(公告)日：2010-01-14
申请号：US12170591
申请日：2008-07-10
申请人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
发明人： Rodney E. Hooker , Colin Eddy , G. Glenn Henry
IPC分类号： G06F15/177 , G06F12/08 , G06F9/44
CPC分类号： G06F1/3203 , G06F9/3017 , G06F9/30189 , G06F9/3814 , G06F9/383 , G06F9/3836 , G06F9/3842 , G06F9/3844 , G06F9/3846 , G06F9/3855 , G06F9/3869
摘要： A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss.
摘要翻译：计算系统包括接收用于配置其操作模式的值的微处理器。设备驱动程序监视当前在微处理器上运行的软件应用程序处于预定列表中并且响应地动态地将值写入微处理器以配置其操作模式。设备驱动程序可以配置的操作模式的示例涉及以下内容：数据预取; 分支预测; 指令缓存驱逐; 指令执行暂停; 高速缓冲存储器的大小，重新排序缓冲器，存储/加载/填充队列; 与数据转发和分支目标地址缓存索引相关的散列算法; 每个时钟周期的指令翻译，格式化和发布的数量; 负载延迟机制; 投机页面指令合并无序执行程度; 缓存非时间暗示数据; 以及响应于指令高速缓存未命中的L2高速缓存和处理器总线的串行或并行访问。

95. 发明授权

US07647479B2 Non-temporal memory reference control mechanism 有权
标题翻译：非时间内存参考控制机制
公开(公告)号：US07647479B2
公开(公告)日：2010-01-12
申请号：US11758515
申请日：2007-06-05
申请人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30185 , G06F9/3824 , G06F12/0862
摘要： An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
摘要翻译：提供了一种用于扩展微处理器指令集以在指令级别指定非时间存储器引用的装置和方法。该装置包括翻译逻辑和扩展执行逻辑。翻译逻辑将扩展指令转换为微指令序列。扩展指令具有扩展前缀和扩展前缀标记。扩展前缀指定由扩展指令规定的存储器引用的非时间访问，其中非时间访问不能由来自现有指令集的现有指令指定。扩展前缀标记指示扩展前缀，其中扩展前缀标记是现有指令集中另外以结构体系指定的操作码。扩展执行逻辑耦合到转换逻辑。扩展执行逻辑接收微指令序列，并执行非时间访问以执行存储器引用。

96. 发明申请

US20090296511A1 MICROPROCESSOR WITH PROGRAM-ACCESSIBLE RE-WRITABLE NON-VOLATILE STATE EMBODIED IN BLOWABLE FUSES OF THE MICROPROCESSOR 有权
标题翻译：具有可编程非可逆非易失性态的微处理器在微处理器的可熔融熔融器中
公开(公告)号：US20090296511A1
公开(公告)日：2009-12-03
申请号：US12141387
申请日：2008-06-18
申请人： G. Glenn Henry , Dinesh K. Jain , Terry Parks
发明人： G. Glenn Henry , Dinesh K. Jain , Terry Parks
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G06F9/30003 , G06F9/3879 , G11C17/18
摘要： A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.
摘要翻译：微处理器包括可由可编程的非易失性状态（RNS），可由微处理器执行的指令寻址，指令微处理器向RNS写入一个新的值。响应于微处理器对指令进行解码，多个保险丝可读取以确定熔丝是熔断还是未吹干。布尔逻辑单元对从多个熔丝读取的值执行布尔运算以确定当前的RNS值。当新值不同于当前值时，保险丝熔断装置会吹动至少一个未熔断的保险丝，将当前RNS值更改为新值。微处理器可以读取多个保险丝，执行布尔运算，并且吹送至少一个未熔断的熔丝，以响应于微处理器执行多次执行指令的程序而将RNS的当前值多次改变为新值。

97. 发明申请

US20090293129A1 TERMINATION OF SECURE EXECUTION MODE IN A MICROPROCESSOR PROVIDING FOR EXECUTION OF SECURE CODE 有权
标题翻译：提供执行安全代码的微处理器安全执行模式终止
公开(公告)号：US20090293129A1
公开(公告)日：2009-11-26
申请号：US12263230
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： H04L9/00 , G06F11/30
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to detect execution of a secure execution mode return event, and that is configured to terminate a secure execution mode within the microprocessor, where the secure execution mode exclusively supports execution of the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program prior to termination of the secure execution mode, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种提供包括微处理器和安全非易失性存储器的安全执行环境的装置。微处理器被配置为执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序。微处理器具有安全执行模式逻辑，其被配置为检测安全执行模式返回事件的执行，并且被配置为终止微处理器内的安全执行模式，其中安全执行模式专门支持安全应用程序的执行。安全非易失性存储器经由专用总线耦合到微处理器，并被配置为在安全执行模式终止之前存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务是从系统总线和微处理器内的相应系统总线资源隔离。

98. 发明申请

US20090292904A1 APPARATUS AND METHOD FOR DISABLING A MICROPROCESSOR THAT PROVIDES FOR A SECURE EXECUTION MODE 有权
标题翻译：用于消除为安全执行模式提供的微处理器的装置和方法
公开(公告)号：US20090292904A1
公开(公告)日：2009-11-26
申请号：US12263244
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that is configured to transfer program control to one of a plurality of event handlers within the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种提供包括微处理器和安全非易失性存储器的安全执行环境的装置。微处理器执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序，并且安全应用程序以安全执行模式执行。微处理器具有安全的看门狗逻辑，其监视与微处理器和安全应用程序相对应的环境属性，并且被配置为将程序控制传送到安全应用程序内的多个事件处理程序之一。安全的非易失性存储器经由专用总线耦合到微处理器。安全非易失性存储器被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和微处理器内的对应系统总线资源隔离。

99. 发明申请

US20090292847A1 MICROPROCESSOR APPARATUS PROVIDING FOR SECURE INTERRUPTS AND EXCEPTIONS 有权
标题翻译：提供安全中断和例外的微处理器设备
公开(公告)号：US20090292847A1
公开(公告)日：2009-11-26
申请号：US12263154
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F13/24
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode. The secure execution mode interrupt logic provides secure interrupts when the microprocessor is operating in a secure mode, where the secure execution mode interrupt logic cannot be observed or accessed by the system bus resources or the non-secure application programs.
摘要翻译：一种用于执行安全代码的装置，具有经由专用总线经由系统总线与系统存储器耦合到安全非易失性存储器的微处理器。微处理器执行非安全应用程序和安全应用程序。微处理器通过专用总线实现专用总线交易，以访问安全非易失性存储器内的安全应用程序。专用总线事务隐藏在与系统总线相连的系统总线资源和设备上。微处理器包括正常的中断逻辑和安全的执行模式中断逻辑。当微处理器以非安全模式运行时，正常的中断逻辑提供用于中断非安全应用程序的非安全中断。当微处理器以安全模式工作时，安全执行模式中断逻辑提供安全中断，其中安全执行模式中断逻辑不能由系统总线资源或非安全应用程序访问。

100. 发明授权

US07539876B2 Apparatus and method for generating a cryptographic key schedule in a microprocessor 有权
标题翻译：用于在微处理器中产生加密密钥调度的装置和方法
公开(公告)号：US07539876B2
公开(公告)日：2009-05-26
申请号：US10826632
申请日：2004-04-16
申请人： G. Glenn Henry , Thomas A. Crispin , Timothy A. Elliott , Terry Parks
发明人： G. Glenn Henry , Thomas A. Crispin , Timothy A. Elliott , Terry Parks
IPC分类号： H04L9/06
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0631 , H04L9/0637 , H04L9/12 , H04L2209/125 , H04L2209/24
摘要： An apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes fetch logic, keygen logic, and execution logic. The fetch logic is disposed within a microprocessor and receives cryptographic instruction single atomic cryptographic instruction as part of an instruction flow executing on the microprocessor. The cryptographic instruction single atomic cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of the one of the cryptographic operations. The keygen logic is disposed within the microprocessor and is operatively coupled to the single atomic cryptographic instruction. The keygen logic directs the microprocessor to expand the provided cryptographic key into the corresponding key schedule. The execution logic is coupled to the keygen logic. The execution logic is disposed within the microprocessor and expands the provided cryptographic key into the corresponding key schedule.
摘要翻译：一种用于执行密码操作的装置和方法。在一个实施例中，提供了一种用于执行加密操作的装置。该装置包括提取逻辑，密钥生成逻辑和执行逻辑。提取逻辑设置在微处理器内，并接收作为在微处理器上执行的指令流的一部分的加密指令单原子加密指令。加密指令单原子加密指令规定了一个加密操作，并且还规定所提供的加密密钥在执行该加密操作之一期间被扩展为对应的密钥调度表。密钥生成器逻辑设置在微处理器内并且可操作地耦合到单原子加密指令。密钥生成逻辑指示微处理器将提供的加密密钥扩展到相应的密钥调度表中。执行逻辑与keygen逻辑耦合。执行逻辑设置在微处理器内，并将所提供的加密密钥扩展到相应的密钥调度表中。

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