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91. 发明授权

US07647478B2 Suppression of store checking 有权
标题翻译：禁止商店检查
公开(公告)号：US07647478B2
公开(公告)日：2010-01-12
申请号：US11758504
申请日：2007-06-05
申请人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/3812 , G06F9/30185 , G06F9/30189
摘要： An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.
摘要翻译：提供了一种用于扩展微处理器指令集以允许在指令级别选择性地抑制存储检查的装置和方法。该装置包括取指逻辑和翻译逻辑。提取逻辑接收扩展指令。扩展指令具有扩展前缀和扩展前缀标记。扩展前缀指定对扩展指令禁止存储检查。扩展前缀标记是现有指令集中的另一种体系结构操作码。提取逻辑排除了与扩展指令相关联的待处理存储事件的存储检查。翻译逻辑耦合到提取逻辑。翻译逻辑将扩展指令转换成微指令序列，序列指示微处理器在执行规定的操作期间排除存储检查。

92. 发明授权

US07631172B2 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence 有权
标题翻译：响应于非标准返回序列的检测，选择性地覆盖返回堆栈预测的装置和方法
公开(公告)号：US07631172B2
公开(公告)日：2009-12-08
申请号：US11609261
申请日：2006-12-11
申请人： G. Glenn Henry , Thomas C. McDonald
发明人： G. Glenn Henry , Thomas C. McDonald
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3861 , G06F9/3806 , G06F9/3848
摘要： A microprocessor for predicting return instruction target addresses is disclosed. A branch target address cache stores a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and provides a prediction of the target address of the return instruction from the target address predictions and provides a corresponding override indicator from the override indicators. Each has a true value when the return stack has mispredicted the target address of the corresponding return instruction for a most recent execution of the return instruction. A return stack also provides a prediction of the target address of the return instruction. Branch control logic causes the microprocessor to branch to the prediction of the target address provided by the BTAC, and not to the prediction of the target address provided by the return stack, when the override indicator is a true value.
摘要翻译：公开了一种用于预测返回指令目标地址的微处理器。分支目标地址缓存存储多个目标地址预测和对应的多个返回指令的对应的多个覆盖指示符，并且从目标地址预测提供对返回指令的目标地址的预测，并提供相应的覆盖指示符从覆盖指标。当返回堆栈错误地预测了最近执行返回指令的相应返回指令的目标地址时，每个值都具有真实值。返回栈还提供了返回指令的目标地址的预测。分支控制逻辑使得微处理器转移到由BTAC提供的目标地址的预测，而不是当覆盖指示符是真值时对由返回栈提供的目标地址的预测。

93. 发明申请

US20090292902A1 APPARATUS AND METHOD FOR MANAGING A MICROPROCESSOR PROVIDING FOR A SECURE EXECUTION MODE 有权
标题翻译：用于管理提供安全执行模式的微处理器的装置和方法
公开(公告)号：US20090292902A1
公开(公告)日：2009-11-26
申请号：US12263238
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/02
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus. The secure application program executes in a secure execution mode. The microprocessor has secure execution mode logic that monitors conditions corresponding to the microprocessor associated with tampering, and causes the microprocessor to transition to a degraded operating mode from the secure execution mode following detection of a first one or more of the conditions. The degraded operating mode exclusively provides for execution of BIOS instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, stores the secure application program. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种提供包括微处理器和安全非易失性存储器的安全执行环境的装置。微处理器执行非安全应用程序和安全应用程序。通过系统总线从系统存储器访问非安全应用程序。安全应用程序以安全执行模式执行。微处理器具有安全的执行模式逻辑，其监视与篡改相关联的微处理器的状况，并且在检测到第一个或多个条件之后使微处理器从安全执行模式转换到降级操作模式。降级的操作模式专门用于执行BIOS指令。安全的非易失性存储器经由专用总线耦合到微处理器，存储安全应用程序。专用总线上的交易与系统总线和微处理器内相应的系统总线资源隔离。

94. 发明申请

US20090292893A1 MICROPROCESSOR HAVING SECURE NON-VOLATILE STORAGE ACCESS 有权
标题翻译：具有安全非易失存储访问权的微处理器
公开(公告)号：US20090292893A1
公开(公告)日：2009-11-26
申请号：US12263131
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种提供安全执行环境的设备。该装置包括微处理器和安全的非易失性存储器。微处理器被配置为执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序。安全的非易失性存储器经由专用总线耦合到微处理器。安全非易失性存储器被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和微处理器内的对应系统总线资源隔离。

95. 发明申请

US20090292853A1 APPARATUS AND METHOD FOR PRECLUDING EXECUTION OF CERTAIN INSTRUCTIONS IN A SECURE EXECUTION MODE MICROPROCESSOR 有权
标题翻译：安全执行模式微处理器预防某些指令执行的装置和方法
公开(公告)号：US20090292853A1
公开(公告)日：2009-11-26
申请号：US12263263
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F13/36
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：提供了一种提供安全执行环境的设备。该装置包括微处理器和安全的非易失性存储器。微处理器被配置为执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序，并且其中以安全执行模式执行安全应用程序。微处理器具有安全执行模式逻辑，其被配置为监视安全应用程序内的指令，并且被配置为排除某些指令的执行。安全非易失性存储器经由专用总线耦合到微处理器，并且被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线隔离，并且对应于微处理器内的系统总线资源。

96. 发明授权

US07562192B2 Microprocessor, apparatus and method for selective prefetch retire 有权
标题翻译：用于选择性预取还原的微处理器，设备和方法
公开(公告)号：US07562192B2
公开(公告)日：2009-07-14
申请号：US11563379
申请日：2006-11-27
申请人： G. Glenn Henry , Rodney E. Hooker
发明人： G. Glenn Henry , Rodney E. Hooker
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/121 , G06F2212/6022
摘要： An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor also includes a cache memory, comprising an array of storage elements for storing cache lines, indexed by an index input. One of the storage elements of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer is storing a replacement candidate line for the prefetched cache line. The microprocessor also includes control logic that determines whether the replacement candidate line in the cache memory is invalid, and if so, replaces the replacement candidate line in the one of the storage elements with the prefetched cache line from the prefetch buffer.
摘要翻译：公开了一种用于选择性地退出预取高速缓存线的微处理器中的装置。微处理器包括预取缓冲器，其存储从耦合到微处理器的系统存储器预取的高速缓存行。微处理器还包括高速缓冲存储器，其包括用于存储由索引输入索引的高速缓存线的存储元件阵列。由预取缓冲器中存储的预取高速缓存行的地址的索引部分索引的数组的存储元素之一是存储用于预取高速缓存行的替换候选行。微处理器还包括控制逻辑，其确定高速缓冲存储器中的替换候选行是否无效，如果是，则从预取缓冲器中用预取的高速缓存行替换存储元件中的一个存储元素中的替换候选行。

97. 发明申请

US20090031110A1 MICROCODE PATCH EXPANSION MECHANISM 审中-公开
标题翻译： MICROCODE PATCH扩展机制
公开(公告)号：US20090031110A1
公开(公告)日：2009-01-29
申请号：US11782088
申请日：2007-07-24
申请人： G. GLENN HENRY , TERRY PARKS
发明人： G. GLENN HENRY , TERRY PARKS
IPC分类号： G06F15/76
CPC分类号： G06F9/268 , G06F9/30174 , G06F9/328
摘要： A microcode patch expansion mechanism includes a patch RAM, an expansion RAM, and a controller. The patch RAM stores a first plurality of patch instructions. The first plurality is to be executed by the microprocessor in place of one or more micro instructions which are stored in a microcode ROM. The expansion RAM stores a second plurality of patch instructions. The number of the second plurality is greater than the number of the first plurality. The second plurality is to be executed by the microprocessor in place of a second one or more micro instructions which are stored in the microcode ROM. The controller executes an EXPRAM micro instruction directing that one or more of the second plurality of patch instructions be loaded into the patch RAM, and loads the one or more of the second plurality of patch instructions into the patch RAM.
摘要翻译：微代码补丁扩展机制包括补丁RAM，扩展RAM和控制器。补丁RAM存储第一多个补丁指令。第一组数据由微处理器代替存储在微代码ROM中的一个或多个微指令来执行。扩展RAM存储第二多个补丁指令。第二多个的数量大于第一多个的数量。第二组数据由微处理器代替存储在微代码ROM中的第二个一个或多个微指令执行。控制器执行EXPRAM微指令，指示将第二多个补丁指令中的一个或多个加载到补丁RAM中，并且将第二多个补丁指令中的一个或多个加载到补丁RAM中。

98. 发明申请

US20090031108A1 CONFIGURABLE FUSE MECHANISM FOR IMPLEMENTING MICROCODE PATCHES 审中-公开
标题翻译：用于实现MICROCODE PATCHES的可配置的保险丝机制
公开(公告)号：US20090031108A1
公开(公告)日：2009-01-29
申请号：US11782105
申请日：2007-07-24
申请人： G. GLENN HENRY , TERRY PARKS
发明人： G. GLENN HENRY , TERRY PARKS
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3017 , G06F9/30189 , G06F9/328
摘要： A patch apparatus includes fuse banks, one or more configuration fuse banks, and an array controller. The fuse banks are configured to store associated patch records that are employed to patch microcode or machine state circuits in the microprocessor or to store associated control data entities that are employed to program control circuits in the microprocessor. The configuration fuse banks are encoded to indicate whether each of the plurality of fuse banks is programmed with one of the associated patch records or with one of the associated control data entities. The array controller reads the fuse banks, and provides the associated patch records to a patch loader or the associated control data entities to control circuits in the microprocessor. The patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM.
摘要翻译：贴片装置包括熔丝组，一个或多个配置熔丝组和阵列控制器。保险丝组被配置为存储用于补偿微处理器中的微代码或机器状态电路的相关补丁记录，或者存储用于对微处理器中的控制电路进行编程的相关联的控制数据实体。配置保险丝组被编码以指示多个保险丝库中的每一个是否用相关联的补丁记录中的一个或与相关联的控制数据实体之一编程。阵列控制器读取熔丝组，并将相关的补丁记录提供给补丁加载器或关联的控制数据实体以控制微处理器中的电路。补丁加载程序根据规定向相应的补丁记录提供与微处理器中的指定目标补丁机制相对应的补丁。补丁加载器在微处理器复位信号转换之后，以及执行存储在BIOS ROM中的指令之前，向指定的目标补丁机制提供补丁。

99. 发明申请

US20090031107A1 ON-CHIP MEMORY PROVIDING FOR MICROCODE PATCH OVERLAY AND CONSTANT UPDATE FUNCTIONS 审中-公开
标题翻译：提供微控制覆盖和持续更新功能的片上存储器
公开(公告)号：US20090031107A1
公开(公告)日：2009-01-29
申请号：US11782094
申请日：2007-07-24
申请人： G. GLENN HENRY , TERRY PARKS
发明人： G. GLENN HENRY , TERRY PARKS
IPC分类号： G06F15/78
CPC分类号： G06F9/328 , G06F8/66 , G06F9/24 , G06F9/268 , G06F9/30149 , G06F9/30174
摘要： A patch mechanism in a microprocessor is provided. The patch mechanism includes an expansion RAM and a patch loader. The expansion RAM stores a plurality of patches, where a first one or more of the plurality of patches are to be executed by the microprocessor in place of a corresponding one or more micro instructions which are stored in a microcode ROM, and where a second one or more of the plurality of patches are employed to patch a corresponding one or more machine states in the microprocessor. The patch loader is coupled to the expansion RAM, and is configured to retrieve the plurality of patches from a source external to the microprocessor, and is configured to load the plurality of patches into the expansion RAM.
摘要翻译：提供微处理器中的贴片机构。补丁机制包括扩展RAM和补丁加载程序。扩展RAM存储多个补丁，其中多个补丁中的第一个或多个补丁将由微处理器代替存储在微代码ROM中的对应的一个或多个微指令，并且其中第二个补丁使用多个补丁中的多个补丁来修补微处理器中相应的一个或多个机器状态。补丁加载器耦合到扩展RAM，并且被配置为从微处理器外部的源检索多个补丁，并且被配置为将多个补丁加载到扩展RAM中。

100. 发明申请

US20090031103A1 MECHANISM FOR IMPLEMENTING A MICROCODE PATCH DURING FABRICATION 审中-公开
标题翻译：用于在制造过程中实现麦克风配对的机构
公开(公告)号：US20090031103A1
公开(公告)日：2009-01-29
申请号：US11782099
申请日：2007-07-24
申请人： G. GLENN HENRY , TERRY PARKS
发明人： G. GLENN HENRY , TERRY PARKS
IPC分类号： G06F15/76
CPC分类号： G06F9/24 , G06F8/60 , G06F9/30174 , G06F9/328 , G06F9/4403
摘要： A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated patch records that are employed to patch microcode or circuits in the microprocessor. The array controller is coupled to the plurality of fuse banks, and is configured to read the associated patch records, and is configured to provide the associated patch records to a patch loader, where the patch loader provides patches corresponding to the associated patch records, as prescribed, to designated target patch mechanisms in the microprocessor. The patch loader provides the patches to the designated target patch mechanisms following transition of a microprocessor reset signal and prior to execution of instructions stored in a BIOS ROM.
摘要翻译：提供微处理器中的贴片装置。贴片装置包括多个保险丝组和阵列控制器。多个熔丝组被配置为存储用于补偿微处理器中的微代码或电路的相关补丁记录。阵列控制器耦合到多个熔丝组，并且被配置为读取相关联的补丁记录，并且被配置为向补丁加载程序提供关联的补丁记录，其中补丁加载程序将对应于关联补丁记录的修补程序提供为规定到微处理器中的指定的目标补丁机制。补丁加载器在微处理器复位信号转换之后，以及执行存储在BIOS ROM中的指令之前，向指定的目标补丁机制提供补丁。

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