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91. 发明授权

US09306003B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09306003B2
公开(公告)日：2016-04-05
申请号：US14396709
申请日：2014-08-15
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Jing Xu , Jiang Yan , Bangming Chen , Hongli Wang , Bo Tang , Zhaoyun Tang , Yefeng Xu , Chunlong Li , Mengmeng Yang
IPC分类号： H01L29/06 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/306
CPC分类号： H01L29/0653 , H01L21/02236 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/76264 , H01L29/0649 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/7833 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78654 , H01L29/78687 , H01L29/78696
摘要： A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.
摘要翻译：一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。

92. 发明授权

US09263581B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09263581B2
公开(公告)日：2016-02-16
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/265 , H01L21/324 , H01L29/06
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

93. 发明申请

US20150380297A1 METHOD FOR MANUFACTURING MOSFET 审中-公开
标题翻译：制造MOSFET的方法
公开(公告)号：US20150380297A1
公开(公告)日：2015-12-31
申请号：US14759324
申请日：2012-10-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Haizhou YIN , Changliang QIN , Huilong ZHU
IPC分类号： H01L21/762 , H01L21/311 , H01L29/16 , H01L29/06 , H01L29/66
CPC分类号： H01L21/76232 , H01L21/31144 , H01L21/76283 , H01L29/045 , H01L29/0657 , H01L29/1608 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Provided is a method for manufacturing a MOSFET, comprising: epitaxially growing a first semiconductor layer on a semiconductor substrate; epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a shallow trench isolation in the first semiconductor layer and the second semiconductor layer to define an active region for the MOSFET; forming on the second semiconductor layer a gate stack and a spacer surrounding the gate stack; forming openings in the second semiconductor layer using the shallow trench isolation, the gate stack and the spacer as a hard mask; epitaxially growing, in each of the openings, a third semiconductor layer using a bottom surface and sidewalls of the opening as a growth seed layer, wherein the third semiconductor layer comprises a material different from that of the second semiconductor layer; and performing ion implantation into the third semiconductor layer to form source and drain regions.
摘要翻译：提供一种用于制造MOSFET的方法，包括：在半导体衬底上外延生长第一半导体层; 在所述第一半导体层上外延生长第二半导体层; 在所述第一半导体层和所述第二半导体层中形成浅沟槽隔离以限定所述MOSFET的有源区; 在所述第二半导体层上形成栅极堆叠和围绕所述栅极叠层的间隔区; 使用浅沟槽隔离在第二半导体层中形成开口，栅极堆叠和间隔物作为硬掩模; 在每个开口中外延生长使用底表面和开口侧壁作为生长种子层的第三半导体层，其中第三半导体层包括与第二半导体层不同的材料; 以及对所述第三半导体层进行离子注入以形成源区和漏区。

94. 发明授权

US09178070B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09178070B2
公开(公告)日：2015-11-03
申请号：US13138053
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/42384 , H01L29/66772 , H01L29/78603
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程，更高的集成度，更低的制造成本。此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

95. 发明授权

US09147745B2 Semiconductor devices formed using a sacrificial layer and methods for manufacturing the same 有权
标题翻译：使用牺牲层形成的半导体器件及其制造方法
公开(公告)号：US09147745B2
公开(公告)日：2015-09-29
申请号：US13981808
申请日：2012-07-24
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786 , H01L21/28 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/2815 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78639 , H01L29/78654
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。

96. 发明授权

US09064954B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09064954B2
公开(公告)日：2015-06-23
申请号：US13623567
申请日：2012-09-20
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7816 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835 , H01L29/7848
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，一种方法包括在衬底上形成第一屏蔽层。该方法还包括以第一屏蔽层为掩模形成应力的源区和漏区中的一个。该方法还包括在衬底上形成第二屏蔽层，并且以第二屏蔽层作为掩模形成源区和漏区中的另一个。该方法还包括去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。该方法还包括形成栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

97. 发明授权

US09047935B2 Read timing generation circuit 有权
标题翻译：读定时生成电路
公开(公告)号：US09047935B2
公开(公告)日：2015-06-02
申请号：US14123104
申请日：2011-11-25
申请人： Weiwei Chen , Lan Chen , Shiyang Yang
发明人： Weiwei Chen , Lan Chen , Shiyang Yang
IPC分类号： G11C7/00 , G11C7/22 , G11C8/18 , G11C8/06 , G11C7/12
CPC分类号： G11C7/222 , G11C7/12 , G11C8/06 , G11C8/18
摘要： Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit.
摘要翻译：公开了能够降低动态功耗的读定时生成电路。经过多位地址Add1，Add2，。。。，AddN通过地址变更监视部（100），生成与该地址对应的响应脉冲信号。在响应脉冲信号通过地址触发判定单元（200）之后，产生单个触发判定信号ATDPRE。单个触发判定信号ATDPRE通过ATD定时生成单元（300）和后定时生成单元（1000），从而在串行链路中形成读取定时生成电路并生成对应的读取定时。与常规读取定时生成电路相比，地址信号的每个位分别对应于执行触发，ATD控制定时输出和ATD确定处理的结构的一级，本发明大大降低了总体动态功耗电路。

98. 发明授权

US09023706B2 Transistor and method for forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US09023706B2
公开(公告)日：2015-05-05
申请号：US14023426
申请日：2013-09-10
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/66 , H01L29/78 , H01L21/265 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26513 , H01L21/2654 , H01L21/26546 , H01L21/823807 , H01L21/823814 , H01L29/517 , H01L29/518 , H01L29/7848
摘要： The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
摘要翻译：晶体管及其形成方法技术领域本发明涉及晶体管及其形成方法。本发明的晶体管包括半导体衬底; 形成在所述半导体衬底上的栅介电层; 形成在栅介质层上的栅极; 栅介电层下的沟道区; 以及位于所述半导体衬底中以及在所述沟道区的相应侧上的源极区和漏极区，其中所述源极和漏极区中的至少一个包括与所述沟道区相邻并且沿垂直方向布置的一组位错到半导体衬底的顶表面，并且该位错集包括至少两个位错。

99. 发明授权

US09013918B2 Two-terminal memory cell and semiconductor memory device based on different states of stable current 有权
标题翻译：基于不同稳态电流的双端存储单元和半导体存储器件
公开(公告)号：US09013918B2
公开(公告)日：2015-04-21
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/39 , G11C17/06 , H01L27/102
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.
摘要翻译：双端存储单元包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来将第一数据状态存储在存储单元中。可以通过在第一P型半导体层和第二N型半导体层之间施加接近存储单元的反向击穿区域的反向偏压来将第二数据状态存储在存储单元中。以这种方式，存储单元可以有效地用于数据存储。

100. 发明授权

US08969930B2 Gate stack structure, semiconductor device and method for manufacturing the same 有权
标题翻译：栅叠层结构，半导体器件及其制造方法
公开(公告)号：US08969930B2
公开(公告)日：2015-03-03
申请号：US13321886
申请日：2011-04-06
申请人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28247 , H01L29/66545 , H01L29/78
摘要： A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.
摘要翻译：栅极堆叠结构包括形成在栅极上并嵌入栅极中的隔离电介质层。侧壁间隔物覆盖隔离电介质层的相对侧面，并且位于有源区上的隔离电介质层比位于连接区上的隔离电介质层厚。一种用于制造栅极堆叠结构的方法包括去除栅极的一部分厚度，有源区上的栅极的去除部分的厚度大于连接区域上的栅极的去除部分的厚度，以便露出侧壁间隔件的相对的内壁; 在栅极上形成隔离电介质层以覆盖暴露的内壁。还提供了一种半导体器件及其制造方法。该方法可以降低栅极和第二接触孔之间发生短路的可能性，并且可以与双接触孔工艺兼容。

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