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91. 发明授权

US4912435A Low-voltage oscillator with separate startup mode 失效
标题翻译：具有独立启动模式的低压振荡器
公开(公告)号：US4912435A
公开(公告)日：1990-03-27
申请号：US404943
申请日：1989-09-07
申请人： Clark R. Williams , Ching-Lin Jiang
发明人： Clark R. Williams , Ching-Lin Jiang
IPC分类号： H03B5/36 , H03K3/014 , H03K3/354 , H03L3/00
CPC分类号： H03B5/06 , H03B5/364 , H03K3/014 , H03K3/3545 , H03L3/00 , H03B2200/0012
摘要： A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.
摘要翻译：一种低功率晶体控制CMOS振荡器，其中在输出放大器的第一级提供长而宽的附加晶体管。这可以防止输出放大器在启动期间从初级放大器级转移太多的电流。

92. 发明授权

US4906588A Enclosed buried channel transistor 失效
标题翻译：封闭式通道晶体管
公开(公告)号：US4906588A
公开(公告)日：1990-03-06
申请号：US210242
申请日：1988-06-23
申请人： Thomas E. Harrington, III
发明人： Thomas E. Harrington, III
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/823807 , H01L29/0646 , H01L29/6659 , H01L29/7838 , H01L27/0922 , H01L27/0928
摘要： An enclosed buried channel device includes a buried channel region (26) disposed under a gate electrode (24). Source and drain regions (54) and (56) are formed on either side of gate electrode (26). The source/drain regions (54) and (56) are separated from the various channel region (26) by isolating regions of N-type material (58) and (60), respectively. The isolating regions (58) and (60) are operable to be inverted during normal operation of the transistor when the transistor is conducting, but are operable to isolate fields on the drain side of the transistor from the buried channel region (26) to lower the leakage current of the device in the off state.
摘要翻译：封闭的埋入通道器件包括设置在栅电极（24）下方的掩埋沟道区（26）。源极和漏极区（54）和（56）形成在栅电极（26）的两侧。通过隔离N型材料（58）和（60）的区域，源极/漏极区域（54）和（56）与各个沟道区域（26）分离。当晶体管导通时，隔离区域（58）和（60）可在晶体管的正常操作期间被反相，但是可操作地将晶体管的漏极侧的场与掩埋沟道区域（26）隔离成较低该器件处于关断状态的漏电流。

93. 发明授权

US4897860A Programmable time base circuit with protected internal calibration 失效
标题翻译：可编程时基电路，具有受保护的内部校准
公开(公告)号：US4897860A
公开(公告)日：1990-01-30
申请号：US163279
申请日：1988-03-02
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： G04F1/00 , G04G3/02 , G11C7/24
CPC分类号： G11C7/24 , G04F1/005 , G04G3/02
摘要： A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).
摘要翻译：具有内部校准的超时电路包括用于产生用于由模n计数器（20）划分的初始频率的振荡器（11）。计数器（20）从校准寄存器（22）接收n的值，并将振荡器的频率除以n的值。门（26）防止寄存器（22）的内容的改变。计数器（20）的输出提供校准频率，进一步由日间计数器（32）除以输出到倒数计数器（34）。倒计时计数器（34）提供由日间计数器（32）输出的信号的预定倒计时，并且在计数结束时产生超时信号。预定的倒计时值由存储在可由客户锁定电路（42）保护的寄存器（36）中的值确定。

94. 发明授权

US4876465A Dynamic CMOS buffer for low current switching 失效
标题翻译：用于低电流切换的动态CMOS缓冲器
公开(公告)号：US4876465A
公开(公告)日：1989-10-24
申请号：US208287
申请日：1988-06-17
申请人： William J. Podkowa , Clark R. Williams
发明人： William J. Podkowa , Clark R. Williams
IPC分类号： H03K19/0185
CPC分类号： H03K19/01855
摘要： A sense circuit for sensing the transition of an input signal from a first logic state to a second logic state and making a corresponding logic transition on the output at a higher slew rate includes a first buffer stage having a complementary pair of transistors consisting of P-channel transistor (34) and N-channel transistor (32) having the drains thereof isolated by N-channel transistor (26). A precharge signal is connected to the gates of the transistors (34) and (32) to turn on transistor (32) and pull the drain thereof low. The drain of transistor (32) is connected to the gate of N-channel transistor (36). The P-channel transistor (26) is connected to an input signal and is operable to connect the drain of transistor (34) to the gate of transistor (36) when transistor (32) is turned off. This results in a node (38) being pulled from a high logic voltage to a low logic voltage when the input signal falls one V.sub.T below the source of transistor (26).
摘要翻译：用于感测输入信号从第一逻辑状态到第二逻辑状态的转换并且以较高的转换速率在输出上进行相应的逻辑转换的感测电路包括：第一缓冲级，具有由P- 沟道晶体管（34）和N沟道晶体管（32），其漏极由N沟道晶体管（26）隔离。预充电信号连接到晶体管（34）和（32）的栅极，以导通晶体管（32）并将其漏极拉低。晶体管（32）的漏极连接到N沟道晶体管（36）的栅极。当晶体管（32）截止时，P沟道晶体管（26）连接到输入信号并可操作以将晶体管（34）的漏极连接到晶体管（36）的栅极。这导致当输入信号在晶体管（26）的源极下降一个VT时，节点（38）从高逻辑电压被拉到低逻辑电压。

95. 发明授权

US4873665A Dual storage cell memory including data transfer circuits 失效
标题翻译：双存储单元存储器，包括数据传输电路
公开(公告)号：US4873665A
公开(公告)日：1989-10-10
申请号：US203424
申请日：1988-06-07
申请人： Ching-Lin Jiang , Clark R. Williams
发明人： Ching-Lin Jiang , Clark R. Williams
IPC分类号： G06F5/06 , G11C8/16 , G11C11/41 , G11C11/412 , G11C19/28
CPC分类号： G11C11/412 , G06F5/065 , G11C11/41 , G11C19/287 , G11C8/16
摘要： A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.
摘要翻译：双存储单元存储器包括双存储单元的阵列，每个双存储单元包含第一存储单元和第二存储单元。第一和第二存储器单元是众所周知的六晶体管静态存储单元，其具有用于将数据直接从每个存储器单元的内部数据节点传送到其对应的互补存储器单元的传输电路，而不需要使用使能晶体管或与每个双存储单元相关联的位线。

96. 发明授权

US4870401A Electronic key locking circuitry 失效
标题翻译：电子钥匙锁定电路
公开(公告)号：US4870401A
公开(公告)日：1989-09-26
申请号：US163281
申请日：1988-03-02
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： G07C9/00 , G11C7/24
CPC分类号： G11C7/24 , G07C9/00857
摘要： An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key,(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands,(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands,(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands,(4) The electronic key is then shipped to an end user. The first valid command recognized by the electronic key, after the R-S flip-flop has been set, starts the countdown timer,(5) After the countdown timer has timed out, the number of valid commands is further reduced. Thus, the key will now respond only to a fourth (very small) set of valid commands.
摘要翻译：根据电子钥匙内某些电路的状态，电子钥匙在其寿命期内对不同的有效命令集进行响应，（1）电子钥匙在初始制作之后，识别第一组有效命令并忽略所有其他命令，（2）在电子钥匙被测试并且电子钥匙中的倒计时电路已被校准之后，电子钥匙内部的定影元件被熔断。这减少了电子钥匙可识别的有效命令的数量。因此，现在的密钥现在仅限于第二组有效的命令，（3）电子钥匙然后运送到OEM，他们将数据编入密钥，并对倒数计时器的时间长度进行编程。然后，OEM在电子钥匙中设置一个R-S触发器，这导致第二组命令中的某些被忽略。因此，密钥现在将仅响应第三组有效命令，（4）电子钥匙然后发送给最终用户。电子钥匙识别的第一个有效指令，在R-S触发器置1之后，启动倒数计时器，（5）倒数计时器超时后，有效命令数进一步减少。因此，密钥现在将仅响应第四（非常小）的有效命令集。

97. 发明授权

US4866301A Controlled slew peak detector 失效
标题翻译：控制摆频峰值检测器
公开(公告)号：US4866301A
公开(公告)日：1989-09-12
申请号：US198166
申请日：1988-05-24
申请人： Michael D. Smith
发明人： Michael D. Smith
IPC分类号： G01R19/04 , H03K5/1532
CPC分类号： H03K5/1532 , G01R19/04
摘要： A peak detector circuit utilizes a comparator to compare an input signal to a peak voltage output signal. The output of the comparator enables a charging current source to charge a holding capacitor at a first rate when the input signal is greater than the peak voltage output signal and enables a discharging current source to discharge the holding capacitor at a second rate when the input signal is less than the peak voltage output signal. The capacitor voltage is coupled through the gate to source of an n-channel transistor and this source voltage forms the peak voltage output signal.
摘要翻译：峰值检测器电路利用比较器将输入信号与峰值电压输出信号进行比较。当输入信号大于峰值电压输出信号时，比较器的输出使得充电电流源能够以第一速率对保持电容器充电，并且使得放电电流源能够以第二速率放电保持电容器，当输入信号小于峰值电压输出信号。电容电压通过n沟道晶体管的栅极与源极耦合，该源极电压形成峰值电压输出信号。

98. 外观设计

USD301713S Portable memory module 失效
公开(公告)号：USD301713S
公开(公告)日：1989-06-20
申请号：US792961
申请日：1985-10-30
申请人： Michael L. Bolan , Francis A. Scherpenberg , William F. Davies, Jr.
设计人： Michael L. Bolan , Francis A. Scherpenberg , William F. Davies, Jr.

99. 发明授权

US4746823A Voltage-insensitive and temperature-compensated delay circuit for a monolithic integrated circuit 失效
标题翻译：用于单片集成电路的电压不敏感和温度补偿延迟电路
公开(公告)号：US4746823A
公开(公告)日：1988-05-24
申请号：US881136
申请日：1986-07-02
申请人： Robert D. Lee
发明人： Robert D. Lee
IPC分类号： H03K5/04 , H03K5/13 , H03K3/26 , H03K17/56
CPC分类号： H03K5/04
摘要： A delay circuit which is insensitive to variations in power supply voltage, which is temperature-compensated, and which is suitable for fabrication in a monolithic integrated circuit includes circuitry for charging a capacitive element through a resistive element from GND toward the power supply voltage. The voltage across the capacitive element is compared to a reference voltage by a voltage comparator, and the voltage comparator generates an output signal when the voltage on the capacitor becomes greater than the reference voltage. The reference voltage for the comparator is generated by a resistor divider connected between GND and the power supply voltage. Inasmuch as the reference voltage varies with changes in the power supply voltage in such a manner as to be maintained at a substantially fixed percentage of the power supply voltage, the time delay provided by the delay circuit is essentially independent of variations in power supply voltage. By utilizing resistors in the resistor divider that have differing temperature coefficients of resistance, the reference voltage for the comparator can be increased and decreased in a predetermined manner in response to increases and decreases in ambient temperature, allowing the time delay of the delay circuit to be adjusted in a predetermined manner as a function of temperature.
摘要翻译：对温度补偿的电源电压变化不敏感的延迟电路，其适用于单片集成电路中的制造，包括用于通过电阻元件从GND朝向电源电压对电容元件充电的电路。通过电压比较器将电容元件两端的电压与参考电压进行比较，当电容上的电压变得大于参考电压时，电压比较器产生一个输出信号。比较器的参考电压由连接在GND和电源电压之间的电阻分压器产生。由于参考电压随着电源电压的变化而变化，从而保持在电源电压的基本上固定的百分比，由延迟电路提供的时间延迟基本上与供电电压的变化无关。通过利用具有不同的电阻温度系数的电阻器分压器中的电阻，可以响应于环境温度的增加和减小以预定方式增加和减小比较器的参考电压，从而允许延迟电路的时间延迟为作为温度的函数以预定方式调节。

100. 发明授权

US4654829A Portable, non-volatile read/write memory module 失效
标题翻译：便携式，非易失性读/写存储器模块
公开(公告)号：US4654829A
公开(公告)日：1987-03-31
申请号：US682701
申请日：1984-12-17
申请人： Ching-Lin Jiang , Robert D. Lee
发明人： Ching-Lin Jiang , Robert D. Lee
IPC分类号： G11C5/00 , G11C5/14 , G11C7/24 , G11C13/00
CPC分类号： G11C5/141 , G11C5/00 , G11C7/24
摘要： A portable, non-volatile read/write memory module includes a battery for providing standby power that is coupled to a monolithic integrated circuit. Five terminals of the module are removably connected to a host electronic system for transfer of data to and from the module. One of the terminals is a chip enable input that may optionally be used for providing operating power to the monolithic integrated circuit. The monolithic integrated circuit further includes control circuitry that may optionally be coded for providing a security feature for access to data stored in the memory module.
摘要翻译：便携式非易失性读/写存储器模块包括用于提供耦合到单片集成电路的待机功率的电池。模块的五个端子可拆卸地连接到主机电子系统，用于将数据传送到模块和从模块传输数据。其中一个端子是芯片使能输入，其可以可选地用于向单片集成电路提供工作电源。单片集成电路还包括控制电路，其可选地被编码以提供用于访问存储在存储器模块中的数据的安全特征。

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