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1. 发明申请

US20040128580A1 Method and apparatus for flexible and programmable clock crossing control with dynamic compensation 有权
标题翻译：用于灵活可编程时钟交叉控制与动态补偿的方法和装置
公开(公告)号：US20040128580A1
公开(公告)日：2004-07-01
申请号：US10335418
申请日：2002-12-30
发明人： Sridhar Ramaswamy , Amit Bodas , Zohar B. Bogin , David E. Freker , Suryaprasad R. Kareenahalli
IPC分类号： G06F005/06
CPC分类号： G06F5/06 , G11C7/22 , G11C7/222
摘要： A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.
摘要翻译：公开了一种从源时钟到目的地时钟的时钟交叉的系统和方法。在一个实施例中，源时钟相位使能信号用于使得一组锁存器组件能够选择性地输入源时钟脉冲。锁存器组件的输出可以由多路复用器根据目的时钟的相位来选择。在另一个实施例中，可以将时间延迟传递到目的时钟域，并且可以通过多个目的地时钟周期时间周期来计算。在某些情况下，可以调整时间延迟以补偿时钟跨越处理中的更长的延迟。

2. 发明申请

US20030229816A1 Clock control arrangement for a computing system, power management system and processing unit including the same 审中-公开
标题翻译：用于计算系统的时钟控制装置，电源管理系统和包括其的处理单元
公开(公告)号：US20030229816A1
公开(公告)日：2003-12-11
申请号：US10373649
申请日：2003-02-24
发明人： Olivier Meynard
IPC分类号： G06F005/06
CPC分类号： G06F1/3215 , G06F1/206 , G06F1/324 , Y02D10/126
摘要： A computing system including a computing unit, such as a processor for instance, which is driven by a clocking arrangement generating at least a first clock having a first value, and a second clock having a higher frequency value which is used for an alternate clocking system. The system includes hardware detection means for analysis the number of transactions existing on the processing bus of the processor for the purpose of detecting a temporary high activity or saturation of the processing unit, and means active in response of said detection for switching the clocking of the processor to said second clock. The clock control may be used for either providing an effective power management system or also a safe overclock control of the speed of the processor. A new arrangement of a processing chip having a overclock request control lead is provided.
摘要翻译：一种计算系统，包括诸如处理器的计算单元，所述计算单元由产生至少具有第一值的第一时钟的计时装置驱动，以及具有较高频率值的第二时钟，所述第二时钟用于替代计时系统。该系统包括硬件检测装置，用于分析存在于处理器的处理总线上的事务的数量，以便检测处理单元的临时高活动或饱和度，以及响应于所述检测来激活以切换处理器到第二个时钟。时钟控制可以用于提供有效的电源管理系统或者用于对处理器的速度进行安全的超频控制。提供了具有超频请求控制线的处理芯片的新配置。

3. 发明申请

US20020029356A1 Input data processing circuit 失效
标题翻译：输入数据处理电路
公开(公告)号：US20020029356A1
公开(公告)日：2002-03-07
申请号：US09946467
申请日：2001-09-06
申请人： NEC CORPORATION
发明人： Hideaki Takahashi
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06 , G06F003/00 , G06F003/02
CPC分类号： G06F5/06 , G06F11/1675
摘要： An input data processing circuit according to one aspect of the present invention comprises a phase detector 50 adapted to detect a clock phase difference between the first and second clocks which are sent from doubled circuits. The readout circuitry 60 selects one of the first and second FIFO buffers (10 or 30) if the clock phase difference is greater than a predetermined time corresponding to a half of data length of the frame, namely, nullmnull bytes of the input data sets. In this case, the selected FIFO buffer (10 or 30) has a faster clock by the clock phase difference than another clock between the first and second clocks. Then the readout circuitry 60 reads the frame out of only the selected FIFO buffer. As the results, no occurrence of nulldata lacknull in FIFO buffers even if a clock rate difference exists between clocks generated by doubled circuits.
摘要翻译：根据本发明的一个方面的输入数据处理电路包括：相位检测器50，用于检测从双重电路发送的第一和第二时钟之间的时钟相位差。如果时钟相位差大于对应于该帧的数据长度的一半的预定时间，则读出电路60选择第一和第二FIFO缓冲器（10或30）中的一个，即输入数据的“m”个字节套。在这种情况下，所选择的FIFO缓冲器（10或30）的时钟相位差比第一和第二时钟之间的时钟频率更快。然后，读出电路60仅从所选择的FIFO缓冲器中读出帧。作为结果，即使在由双电路产生的时钟之间存在时钟速率差，FIFO缓冲器中也不会出现“数据缺失”。

4. 发明申请

US20020013914A1 Frequency sensor for each interface of a data carrier 有权
标题翻译：数据载体的每个接口的频率传感器
公开(公告)号：US20020013914A1
公开(公告)日：2002-01-31
申请号：US09838999
申请日：2001-04-20
发明人： Stefan Posch , Peter Kompan , Peter Thueringer , Wolfgang Meindl , Klaus Ully
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06K19/07769 , G06K19/07 , G06K19/0723 , G06K19/0724
摘要： A data carrier (4) for the transfer of communication data (KD1, KD2) via at least two interface means (11, 12), having first interface means (11) for receiving a first communication signal (KS1), and having second interface means (12) for receiving a second communication signal (KS2), and having processing means (13) to which a first clock signal (TS1) derived from the first communication signal (KS1) or a second clock signal (TS2) derived from the second communication signal (KS2) can be applied for the processing of the transferred communication data (KD1, KD2), and having reset means (21) for resetting the processing by the processing means (13), now includes a first frequency sensor (22) which is adapted to supply first frequency reset information (RI4) to the reset means (21) when a first clock frequency of the first clock signal (TS1) or the frequency (FKS1) of the first communication signal (KS1) lies below a first lower frequency threshold (FU1), and includes a second frequency sensor (23) which is adapted to supply second frequency reset information (RI5) to the reset means (21) when a second clock frequency of the second clock signal (TS2) or the frequency (FKS2) of the second communication signal (KS2) lies below a second lower frequency threshold (FU2), the reset means (21) being adapted to reset the processing by the processing means (13) when the first clock signal (TS1) is applied to the processing means (13) and the first frequency reset information (RI4) is received or when the second clock signal (TS2) is applied to the processing means (13) and the second frequency reset information (RI5) is received.
摘要翻译：一种用于经由至少两个接口装置（11,12）传送通信数据（KD1，KD2）的数据载体（4），具有用于接收第一通信信号（KS1）的第一接口装置（11），并具有第二接口用于接收第二通信信号（KS2）的装置（12），以及具有从第一通信信号（KS1）导出的第一时钟信号（TS1）或从第一通信信号（KS1）导出的第二时钟信号（TS2）的处理装置第二通信信号（KS2）可以应用于所传送的通信数据（KD1，KD2）的处理，并且具有用于通过处理装置（13）重新设置处理的复位装置（21），现在包括第一频率传感器），其适于在第一时钟信号（TS1）的第一时钟频率或第一通信信号（KS1）的频率（FKS1）位于第一时钟信号（KS1）的下方时将第一频率复位信息（RI4）提供给复位装置（21）第一低频阈值（FU1），并且包括第二频率传感器（23），当第二时钟信号（TS2）的第二时钟频率或第二通信信号（KS2）的频率（FKS2）为第二时钟频率时，适于向复位装置提供第二频率复位信息（RI5）位于第二较低频率阈值（FU2）之下时，当第一时钟信号（TS1）被施加到处理装置（13）时，复位装置（21）适于复位处理装置（13）的处理，接收频率复位信息（RI4），或者当第二时钟信号（TS2）被施加到处理装置（13）并且接收到第二频率复位信息（RI5）时。

5. 发明申请

US20040117693A1 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US20040117693A1
公开(公告)日：2004-06-17
申请号：US10372970
申请日：2003-02-26
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co., Ltd.
发明人： Naokatsu Moriyama , Shigeru Shinohara
IPC分类号： G06F001/04 , G06F001/06 , G06F001/08 , G06F001/12 , G06F005/06 , G06F011/00
CPC分类号： G06F21/77 , G06F21/55 , G06F21/755
摘要： There is provided a technology for preventing disabling of function of a clock monitoring circuit by a hacker in a microcomputer for IC card provided with a clock monitoring circuit as a countermeasure for a hacker. In the microcomputer for IC card provided with the clock monitoring circuit, the clock monitoring circuit is given the function to perform the detecting operation twice during one cycle, namely at the timings of rise and fall of the clock.
摘要翻译：提供了一种技术，用于防止在设置有时钟监视电路的IC卡的微型计算机中的黑客对时钟监控电路的功能的禁用作为黑客的对策。在设置有时钟监视电路的IC卡的微计算机中，时钟监视电路具有在一个周期内即时钟上升和下降的定时执行两次检测操作的功能。

6. 发明申请

US20040088599A1 Data transmission system, interface control semiconductor integrated circuit and method for controlling protocol circuit 有权
标题翻译：数据传输系统，接口控制半导体集成电路和控制协议电路的方法
公开(公告)号：US20040088599A1
公开(公告)日：2004-05-06
申请号：US10692743
申请日：2003-10-27
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO.
发明人： Takayuki Matsui , Ryougo Yanagisawa , Kiyotaka Iwamoto
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： In an interface control semiconductor integrated circuit including a plurality of protocol circuits for processing a protocol such as AV- or PC-oriented protocols engaged in an IEEE 1394 standard-compliant data transmission, power consumption is reduced. To achieve this, the interface control semiconductor integrated circuit including the protocol circuits is provided with a plurality of switches associated with the respective protocol circuits and each of the switches performs a switching between supply and shut-off of a clock. A clock is supplied to one of the protocol circuits which should be used whereas clock to unused protocol circuits are shut-off, by controlling each of the switches.
摘要翻译：在包括用于处理协议的多个协议电路的接口控制半导体集成电路中，诸如参与符合IEEE 1394标准的数据传输的AV或面向PC的协议，功耗降低。为了实现这一点，包括协议电路的接口控制半导体集成电路设置有与各个协议电路相关联的多个开关，并且每个开关执行时钟的供应和截止之间的切换。通过控制每个开关，将时钟提供给应该使用的协议电路之一，而未使用的协议电路的时钟被切断。

7. 发明申请

US20020188885A1 DMA port sharing bandwidth balancing logic 有权
标题翻译： DMA端口共享带宽平衡逻辑
公开(公告)号：US20020188885A1
公开(公告)日：2002-12-12
申请号：US10047546
申请日：2002-01-16
发明人： Bjorn Sihlbom , Neal S. Stollon , Thomas McCaughey
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06F13/28 , G06F15/7842
摘要： A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.
摘要翻译：具有数字信号处理器和至少一个可编程逻辑核心的异构集成电路。 AMBA AHB将IC和大多数其他功能单元耦合在IC上。 PLC还通过单独的DMA共享单元耦合到DSP，特别是DSP到DSP存储器。存储器共享布置在PLC和DSP之间提供单独的高速数据传输机制。控制内存共享以将DSP存储器的全部带宽与其操作速度成比例地分配给PLC和其他DMA设备。 AMBA AHB允许DSP控制PLC操作，而不会干扰高速数据传输。

8. 发明申请

US20020178393A1 Method of detecting termination of a bus transfer operation 有权
标题翻译：检测总线传输操作终止的方法
公开(公告)号：US20020178393A1
公开(公告)日：2002-11-28
申请号：US10177623
申请日：2002-06-24
发明人： Douglas A. Larson
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06F13/4273
摘要： A method to detect when a bus master device terminates a bus data transfer operation includes providing a first counter clocked by a first clock signal and providing a second counter clocked by a second clock signal. Outputs of the first and second counters are compared, and it is determined if termination of the bus transfer operation has occurred based on comparing the outputs.
摘要翻译：检测总线主设备何时终止总线数据传送操作的方法包括提供由第一时钟信号计时的第一计数器，并提供由第二时钟信号计时的第二计数器。比较第一和第二计数器的输出，并且基于比较输出来确定总线传送操作的终止是否发生。

9. 发明申请

US20020073352A1 Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US20020073352A1
公开(公告)日：2002-06-13
申请号：US09993704
申请日：2001-11-27
发明人： Haruyasu Okubo , Atsushi Kiuchi , Shigezumi Matsui
IPC分类号： G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06F1/3237 , G06F1/3203 , Y02D10/126 , Y02D10/128 , Y02D50/20
摘要： This data processor can satisfy both requests of a fast transition from a low power consumption state to an operating state and low power consumption, and a data processor has a program running state, a standby mode, a light standby mode, and a sleep mode. In the sleep mode, the supply of a synchronizing clock signal to a central processing unit (CPU) is stopped and the synchronizing clock signal is supplied to other circuit modules. In the standby mode, the frequency multiplication and frequency operation of a clock pulse generator are suspended and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the frequency multiplication and frequency division operation of the clock pulse generator are enabled and the supply of the synchronizing clock signal to the CPU and other circuit modules is stopped. In the light standby mode, the transition of the CPU to an instruction executable state is faster than in the standby mode and the lower power consumption than in the sleep mode is obtained.
摘要翻译：该数据处理器可以满足从低功耗状态到操作状态和低功耗的快速转换的请求，并且数据处理器具有程序运行状态，待机模式，光待机模式和睡眠模式。在睡眠模式中，停止向中央处理单元（CPU）提供同步时钟信号，并将同步时钟信号提供给其他电路模块。在待机模式下，暂停时钟脉冲发生器的倍频和频率操作，并停止向CPU和其他电路模块提供同步时钟信号。在光待机模式下，时钟脉冲发生器的倍频和分频操作被使能，并且停止向CPU和其它电路模块提供同步时钟信号。在光待机模式中，CPU到指令可执行状态的转换比在待机模式中快，并且获得的功耗低于休眠模式。

10. 发明申请

US20040049798A1 Computer system and data transmitting method thereof 审中-公开
标题翻译：计算机系统及其数据传输方法
公开(公告)号：US20040049798A1
公开(公告)日：2004-03-11
申请号：US10656110
申请日：2003-09-08
申请人： Samsung Electronics Co., Ltd.
发明人： Ho-Jin Ha
IPC分类号： H04N007/18 , H04N007/173 , H04N007/16 , H04N007/00 , H04N011/00 , G06F001/04 , G06F001/12 , G06F005/06
CPC分类号： G06F1/1601
摘要： The present invention relates to a computer system enabling data stored in a hard disk to be outputted to an external apparatus through a display apparatus and a data transmitting method thereof.
摘要翻译：本发明涉及使存储在硬盘中的数据能够通过显示装置输出到外部装置的计算机系统及其数据发送方法。

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