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1. 发明授权

US07450818B2 Apparatus for recording data, method for recording data and television program receiver 失效
标题翻译：用于记录数据的装置，用于记录数据的方法和电视节目接收器
公开(公告)号：US07450818B2
公开(公告)日：2008-11-11
申请号：US10461677
申请日：2003-06-16
申请人： Shigeyasu Natsubori , Toru Imai , Toshiya Takahashi , Shigeru Oyanagi
发明人： Shigeyasu Natsubori , Toru Imai , Toshiya Takahashi , Shigeru Oyanagi
IPC分类号： H04N5/91
CPC分类号： H04N21/4435 , G11B27/034 , G11B27/036 , G11B27/11 , G11B27/329 , G11B27/36 , G11B2220/20 , G11B2220/65 , H04N5/782 , H04N5/85 , H04N21/4147 , H04N21/4334 , H04N21/47214
摘要： By using program information, the amount of which to be transmitted is not fixed, and related information which is related to the expected amount of the main information, an area for recording main information is ensured in advance on a recording medium. This ensures a reliable recording of a program, the recording of which has already been reserved, without affecting any program which has already been recorded. In addition, even when a change occurs in related information before or after the start of recording information on the recording medium, an area assigned before the start of the recording can be changed corresponding to related information after the change.
摘要翻译：通过使用节目信息，其发送量不固定，并且在记录介质上预先确保与主信息的期望量相关的相关信息，用于记录主信息的区域。这样可以保证对已记录的节目的记录的可靠记录，而不影响已经记录的节目。此外，即使当在记录介质上记录信息开始之前或之后的相关信息发生变化时，可以根据改变之后的相关信息来改变记录开始之前分配的区域。

2. 发明授权

US07606566B2 Mobile communication apparatus having capability of housing temperature control 失效
标题翻译：具有容纳温度控制能力的移动通信装置
公开(公告)号：US07606566B2
公开(公告)日：2009-10-20
申请号：US11384901
申请日：2006-03-20
申请人： Isao Ogoshi
发明人： Isao Ogoshi
IPC分类号： H04W24/00 , H04N5/232
CPC分类号： H04M1/72519 , H04M1/66 , H04M2250/12
摘要： A mobile communication apparatus capable of controlling housing temperature is provided. The mobile communication apparatus includes a first and a second modules, an operating mode manager for managing a plurality of modes based on a combination of whether the first and the second modules each are supplied with power, and a memory for storing a plurality of data relating a period of operating time to a value of housing temperature for each of the modes. The communication apparatus includes a temperature estimator configured to measure the operating time, and if the mode is changed, to estimate a first and a second values of housing temperature corresponding to the operating time of the mode before the change and of the mode after the change respectively, and to have the operating mode manager stop the operation if an estimation based on the first and the second values reaches a predetermined threshold.
摘要翻译：提供了能够控制壳体温度的移动通信装置。移动通信装置包括第一模块和第二模块，用于根据第一模块和第二模块是否被提供电力的组合来管理多种模式的操作模式管理器，以及用于存储多个数据相关的存储器每个模式的运行时间为住房温度值。通信装置包括温度估计器，其被配置为测量操作时间，并且如果模式被改变，则估计与改变之前的模式的操作时间相对应的壳体温度的第一和第二值，以及改变之后的模式的操作时间并且如果基于第一和第二值的估计达到预定阈值，则使操作模式管理器停止操作。

3. 发明授权

US07382653B2 Electrically rewritable non-volatile semiconductor memory device 失效
标题翻译：电可重写非易失性半导体存储器件
公开(公告)号：US07382653B2
公开(公告)日：2008-06-03
申请号：US11566283
申请日：2006-12-04
申请人： Fumitaka Arai , Masayuki Ichige
发明人： Fumitaka Arai , Masayuki Ichige
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A first selection transistor is connected between one end of a memory cell group and a bit line. A second selection transistor which has a gate length shorter than a gate length of the first transistor is connected between the other end of the memory cell group and a source line. In a write, a control gate driver applies a write voltage to the control gate of the memory cell as a write target, and applies an intermediate voltage to the control gates of the other memory cells. A selection gate driver supplies a first voltage lower than the intermediate voltage to the first transistor, and supplies a second voltage lower than the first voltage to the second transistor. A bit line controller supplies the first voltage to the bit line which is not selected for writing, and a source line driver supplies the first voltage to the source line.
摘要翻译：第一选择晶体管连接在存储单元组的一端和位线之间。具有比第一晶体管的栅极长度短的栅极长度的第二选择晶体管连接在存储单元组的另一端和源极线之间。在写入时，控制栅极驱动器将写入电压作为写入目标器施加到存储器单元的控制栅极，并将中间电压施加到其它存储器单元的控制栅极。选择栅极驱动器将低于中间电压的第一电压提供给第一晶体管，并将低于第一电压的第二电压提供给第二晶体管。位线控制器将第一电压提供给未被选择用于写入的位线，并且源极线驱动器将第一电压提供给源极线。

4. 发明授权

US07994584B2 Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer 有权
标题翻译：具有在扩散层上不形成硅化物的非硅化物区域的半导体器件
公开(公告)号：US07994584B2
公开(公告)日：2011-08-09
申请号：US12277456
申请日：2008-11-25
申请人： Takayuki Hiraoka , Kuniaki Utsumi , Tsutomu Kojima , Kenji Honda
发明人： Takayuki Hiraoka , Kuniaki Utsumi , Tsutomu Kojima , Kenji Honda
IPC分类号： H01L21/331
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.
摘要翻译：半导体器件包括对应于至少第一电源电压和低于第一电源电压的第二电源电压的第一和第二MOSFET，以及形成在第一和第二MOSFET的漏极部分中并且不形成在其中的硅化物的非硅化物区域。第一MOSFET包括形成在源极/漏极部分的第一扩散层，形成在栅极部分下方并形成为比第一扩散层浅的第二扩散层，以及形成在第一扩散层中的与第二扩散层相同深度的第三扩散层，硅化物区域，第二MOSFET包括形成在源极/漏极部分的第四扩散层，形成在栅极部分下方并形成为比第四扩散层浅的第五扩散层和形成为比第四扩散层浅的第六扩散层，非硅化物区域中的第五扩散层。

5. 发明授权

US6031991A Debug system and method for reproducing an error occurring in parallel-executed programs 失效
标题翻译：用于再现并行执行程序中发生错误的调试系统和方法
公开(公告)号：US6031991A
公开(公告)日：2000-02-29
申请号：US12240
申请日：1998-01-23
申请人： Hideaki Hirayama
发明人： Hideaki Hirayama
IPC分类号： G06F11/14 , G06F11/28 , G06F11/36 , G06F9/44
CPC分类号： G06F11/3632 , G06F11/366
摘要： A debug system according to the invention is used in a multiprocessor system for executing a plurality of programs while taking check points. This debug system comprises detection section for detecting an error in any of the programs, restart section for shifting the programs to a debug mode and restarting the programs from a check point which has been taken immediately before occurrence of the error, when the detection section has detected the error, and section for executing the programs in the debug mode such that a history of the execution of the restarted programs is reproduced. The programs are again restarted from the check point when a next check point has been reached without reproduction of the error.
摘要翻译：根据本发明的调试系统在多处理器系统中被用于在检查点的同时执行多个程序。该调试系统包括用于检测任何程序中的错误的检测部分，用于将程序移动到调试模式的重新启动部分，并且当检测部分具有检测到错误，以及用于在调试模式中执行程序的部分，使得重新启动的程序的执行历史被再现。当到达下一个检查点而不复制错误时，程序再次从检查点重新启动。

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