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1. 发明授权

US5313110A Monostable multivibrating circuit 失效
标题翻译：单稳态多谐振荡电路
公开(公告)号：US5313110A
公开(公告)日：1994-05-17
申请号：US118686
申请日：1993-09-10
申请人： Yoshio Watanabe , Tatsuaki Kitta
发明人： Yoshio Watanabe , Tatsuaki Kitta
IPC分类号： H03K3/0232 , H03K5/13 , H03K5/1534 , H03K3/284
CPC分类号： H03K5/13 , H03K5/1534
摘要： A monostable multivibrating circuit includes: a time constant setting circuit responsive to an input pulse signal, for outputting at least one signal having a time constant different from that of the input pulse signal; and an emitter-coupled logic circuit including a first pair of transistors, one base receiving the input pulse signal and another base receiving a first reference signal, and a second pair of transistors, one base receiving an output signal of the time constant setting circuit and another base receiving a second reference signal. The monostable multivibrating circuit outputs a one-shot pulse defined by a pulse starting time corresponding to a change in level of the one base input of the first pair of transistors and a pulse stopping time corresponding to a change in level of the one base input of the second pair of transistors. The one-shot pulse presents "H" level only when the base input of the first pair of transistors is at "L" level and the one base input of the second pair of transistors is at "H" level. By this constitution, it is possible to determine the number of stages of circuits regardless of the duration of the one-shot pulse and thus facilitate a standardization of the circuit designing. Also, it is possible to reduce an occupation area thereof and decrease a power dissipation thereby.
摘要翻译：单稳态多谐振电路包括：响应于输入脉冲信号的时间常数设置电路，用于输出具有不同于输入脉冲信号的时间常数的至少一个信号; 以及发射极耦合逻辑电路，包括第一对晶体管，一个基极接收输入脉冲信号，另一个基极接收第一参考信号;第二对晶体管，一个基极接收时间常数设置电路的输出信号;以及另一基站接收第二参考信号。单稳态多谐波电路输出由对应于第一对晶体管的一个基极输入的电平变化的脉冲开始时间定义的单触发脉冲，以及与第一对晶体管的一个基极输入的电平变化相对应的脉冲停止时间第二对晶体管。仅当第一对晶体管的基极输入为“L”电平且第二对晶体管的一个基极输入为“H”电平时，单次脉冲呈现“H”电平。通过这种结构，可以确定电路的级数，而不管单触发脉冲的持续时间如何，从而有助于电路设计的标准化。此外，可以减少其占用面积并由此降低功耗。

2. 发明授权

US08027422B2 Symbol timing recovery circuit 有权
标题翻译：符号定时恢复电路
公开(公告)号：US08027422B2
公开(公告)日：2011-09-27
申请号：US12112757
申请日：2008-04-30
申请人： Tatsuaki Kitta
发明人： Tatsuaki Kitta
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H04L7/0334
摘要： An analog-to-digital (A/D) converter samples an input signal with a first clock. An finite impulse response (FIR) filter generates data at a zero-crossing point/data decision point from the sampled data. A decimation circuit decimates an output of the FIR filter 2 with a second clock. A phase comparator detects a phase error of the output signal of the decimation circuit. An Numerically Controlled Oscillator (NCO) (A/D) generates a phase signal by integrating the phase error. A tap coefficient computing unit generates tap coefficients of the FIR filter in accordance with the phase signal. In the NCO, if the phase signal exceeds “π”, “2π+the phase error” is subtracted from the phase signal.
摘要翻译：模数（A / D）转换器用第一时钟对输入信号进行采样。有限脉冲响应（FIR）滤波器在采样数据的过零点/数据判定点处生成数据。抽取电路用第二时钟抽取FIR滤波器2的输出。相位比较器检测抽取电路的输出信号的相位误差。数控振荡器（NCO）（A / D）通过积分相位误差产生相位信号。抽头系数计算单元根据相位信号产生FIR滤波器的抽头系数。在NCO中，如果相位信号超过“＆pgr”，则从相位信号中减去“2＆pgr + +相位误差”。

3. 发明授权

US06563897B1 Multirate symbol timing recovery circuit 有权
标题翻译：多速率符号定时恢复电路
公开(公告)号：US06563897B1
公开(公告)日：2003-05-13
申请号：US09375212
申请日：1999-08-16
申请人： Tatsuaki Kitta
发明人： Tatsuaki Kitta
IPC分类号： H03D324
CPC分类号： H04L7/0029 , H03L7/081 , H03L7/0994 , H04L7/0335 , H04L2025/03477 , H04L2025/03617
摘要： A symbol timing recovery circuit of the type that controls the phase of a received signal to synchronize it to a clock is capable of accommodating differing symbol rates. Base clock frequency fsamp is divided by N to derive frequency fsamp′, where N is the largest integer contained in a set of integers by any of which the base frequency fsamp can be divided to derive a frequency more than twice as high as symbol rate fs, and sampling clock CLK3 of the frequency fsamp′is used in an FIR filter 20. &Dgr;th is added to the output of a loop filter 38, and the result is supplied to an NCO 42. The value of &Dgr;th is determined from the difference between 2fs and fsamp′.
摘要翻译：控制接收信号的相位以使其与时钟同步的类型的符号定时恢复电路能够适应不同的符号率。基准时钟频率fsamp被除以N以导出频率fsamp'，其中N是包含在一组整数中的最大整数，其中基本频率fsamp中的任何一个可以被分频以导出比符号速率fs高两倍的频率，并且在FIR滤波器20中使用频率fsamp'的采样时钟CLK3。将DELTAth加到环路滤波器38的输出端，并将结果提供给NCO 42. DELTAth的值根据 2fs和fsamp'。

4. 发明授权

US06310925B1 Phase angle detector and frequency discriminator employing the same 有权
标题翻译：相位角检测器和使用它的鉴频器
公开(公告)号：US06310925B1
公开(公告)日：2001-10-30
申请号：US09131879
申请日：1998-08-10
申请人： Tatsuaki Kitta
发明人： Tatsuaki Kitta
IPC分类号： H04L2714
CPC分类号： H04L27/3854
摘要： According to the present invention, in accordance with the first to fourth quadrants on the phase plane for signal points, a phase angle detector converts an I channel signal or a Q channel signal obtained by a demodulator, by using individually set operating expressions, so as to correlate the angle (phase angle) for a signal point on the plane phase with a predetermined one-dimensional coordinate. More specifically, the phase angle that extends from a border point in an arbitrary quadrant on the phase plane to a border position shifted 360° is allocated for a specific one-dimensional coordinate. The coordinate value on the one-dimensional coordinate is calculated by using the operating expression which is set in accordance with the first to the fourth quadrant of the signal point which is detected using the I channel signal and the Q channel signal. This can be an arbitrary expression; however, as simple an operating expression as possible is selected so that the calculation can be performed by as simple a circuit as possible.
摘要翻译：根据本发明，根据用于信号点的相平面上的第一至第四象限，相位角检测器通过使用单独设置的操作表达式来转换由解调器获得的I信道信号或Q信道信号，从而以将平面相位上的信号点的角度（相位角）与预定的一维坐标相关联。更具体地说，对于特定的一维坐标，分配从相位面上的任意象限的边界点向偏移360°的边界位置延伸的相位角。通过使用根据使用I信道信号和Q信道信号检测的信号点的第一至第四象限设置的操作表达式来计算一维坐标上的坐标值。这可以是一个任意表达; 然而，选择尽可能简单的操作表达式使得可以通过尽可能简单的电路来执行计算。

5. 发明授权

US07697637B2 Demodulation circuit and demodulating method 有权
标题翻译：解调电路和解调方法
公开(公告)号：US07697637B2
公开(公告)日：2010-04-13
申请号：US11450465
申请日：2006-06-12
申请人： Tatsuaki Kitta , Takanori Iwamatsu
发明人： Tatsuaki Kitta , Takanori Iwamatsu
IPC分类号： H04L27/00
CPC分类号： H04L27/2067 , H04L7/0029 , H04L7/0054 , H04L2027/0032 , H04L2027/0057 , H04L2027/0067 , H04L2027/0079
摘要： A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.
摘要翻译：尽管频率误差较大，但是解调电路可以执行捕获操作。当载波的相位误差较大并且信号点位于预定位置时，相位比较器输出将除0之外的预定值作为相位误差的确定结果。当确定结果的积分值达到限制器的正最大值时，环路滤波器向积分器输出负最小值。因此，当相位误差大时，从环路滤波器输出从负最小值变化到正最大值的值，从而实现宽的同步捕获范围。

6. 发明申请

US20070172002A1 Demodulation circuit and demodulating method 有权
标题翻译：解调电路和解调方法
公开(公告)号：US20070172002A1
公开(公告)日：2007-07-26
申请号：US11450465
申请日：2006-06-12
申请人： Tatsuaki Kitta , Takanori Iwamatsu
发明人： Tatsuaki Kitta , Takanori Iwamatsu
IPC分类号： H04L27/00 , H04L27/22
CPC分类号： H04L27/2067 , H04L7/0029 , H04L7/0054 , H04L2027/0032 , H04L2027/0057 , H04L2027/0067 , H04L2027/0079
摘要： A demodulation circuit can perform a capturing operation although afrequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.
摘要翻译：虽然频率误差大，但是解调电路可以进行拍摄操作。当载波的相位误差较大并且信号点位于预定位置时，相位比较器输出将除0之外的预定值作为相位误差的确定结果。当确定结果的积分值达到限制器的正最大值时，环路滤波器向积分器输出负最小值。因此，当相位误差大时，从环路滤波器输出从负最小值变化到正最大值的值，从而实现宽的同步捕获范围。

7. 发明申请

US20070172001A1 DEMODULATION CIRCUIT AND DEMODULATION METHOD 审中-公开
标题翻译：解调电路和解调方法
公开(公告)号：US20070172001A1
公开(公告)日：2007-07-26
申请号：US11382490
申请日：2006-05-10
申请人： Tatsuaki Kitta , Takanori Iwamatsu
发明人： Tatsuaki Kitta , Takanori Iwamatsu
IPC分类号： H04L27/00 , H04B1/10
CPC分类号： H04L27/3872 , H04L7/0029 , H04L25/0305 , H04L27/0002
摘要： A demodulation circuit according to the present invention comprises an automatic equalizer for carrying out equalization processing of a signal, a carrier recovery circuit for carrying out carrier recovery processing based on an equalized signal by the automatic equalizer. A center tap for carrying out an amplitude control of the automatic equalizer is placed on an input side thereof, and a control signal to the center tap is transmitted from the automatic equalizer.
摘要翻译：根据本发明的解调电路包括用于执行信号的均衡处理的自动均衡器，用于通过自动均衡器基于均衡信号进行载波恢复处理的载波恢复电路。用于执行自动均衡器的幅度控制的中心抽头被放置在其输入侧，并且从自动均衡器发送到中心抽头的控制信号。

8. 发明授权

US08804806B2 Symbol timing recovery circuit 有权
标题翻译：符号定时恢复电路
公开(公告)号：US08804806B2
公开(公告)日：2014-08-12
申请号：US13533673
申请日：2012-06-26
申请人： Tatsuaki Kitta
发明人： Tatsuaki Kitta
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L27/01 , H04L7/0029 , H04L7/0054 , H04L7/0062 , H04L27/38
摘要： Disclosed is a symbol timing recovery circuit which includes an interpolator to generate, using a first filter, interpolation data of an input signal; a forward equalizer to eliminate, using a second filter, a forward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a first identification signal, and a first error signal; a backward equalizer to eliminate, using a third filter, a backward interference wave from the input signal based on the interpolation data, and to output the resultant signal after the elimination, a second identification signal, and a second error signal; and a timing recovery unit to generate a tap coefficient of the first filter, based on a tap coefficient of the second filter, a tap coefficient of the third filter, the first identification signal, the first error signal, the second identification signal, and the second error signal.
摘要翻译：公开了一种符号定时恢复电路，其包括内插器，用于使用第一滤波器生成输入信号的插值数据; 前向均衡器，用于基于插值数据从输入信号中消除使用第二滤波器的前向干扰波，并且在消除之后输出所得到的信号，第一识别信号和第一误差信号; 反向均衡器，用于根据插值数据从输入信号中消除使用第三滤波器的反向干扰波，并且在消除后输出合成信号，第二识别信号和第二误差信号; 以及定时恢复单元，用于基于第二滤波器的抽头系数，第三滤波器的抽头系数，第一识别信号，第一误差信号，第二识别信号和第二滤波器产生第一滤波器的抽头系数，第二个误差信号。

9. 发明申请

US20050197076A1 Radio communication device and control method of amplification circuit thereof 审中-公开
标题翻译：无线通信装置及其放大电路的控制方法
公开(公告)号：US20050197076A1
公开(公告)日：2005-09-08
申请号：US10898251
申请日：2004-07-26
申请人： Shinji Saito , Tatsuaki Kitta
发明人： Shinji Saito , Tatsuaki Kitta
IPC分类号： H03G3/20 , H01Q11/12 , H03C1/52 , H03G3/30 , H04B1/02 , H04B1/04 , H04J11/00
CPC分类号： H03G3/3042 , H04B2001/0416
摘要： In a radio communication device which generates a baseband signal based on inputted transmit data, then modulates the baseband signal to a modulating signal, amplifies the modulating signal in a modulating circuit, and transmits the amplified modulating signal, a modulating signal control circuit which detects an amplitude of the modulating signal based on a digital baseband signal before DA conversion processing generated in a baseband processing circuit and controls a dynamic range of the amplification circuit based on a result of the detection is provided, and consequently, the amplification circuit can be properly controlled according to the state of a transmit signal by a simple circuit configuration.
摘要翻译：在基于输入的发送数据生成基带信号的无线通信装置中，将基带信号调制为调制信号，放大调制电路中的调制信号，发送放大的调制信号，调制信号控制电路检测提供基于在基带处理电路中生成的DA转换处理之前的数字基带信号的调制信号的幅度，并且基于检测结果控制放大电路的动态范围，因此可以适当地控制放大电路根据通过简单的电路配置发送信号的状态。

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